ATE240008T1 - Skalierung eines emulation-systems - Google Patents

Skalierung eines emulation-systems

Info

Publication number
ATE240008T1
ATE240008T1 AT00910094T AT00910094T ATE240008T1 AT E240008 T1 ATE240008 T1 AT E240008T1 AT 00910094 T AT00910094 T AT 00910094T AT 00910094 T AT00910094 T AT 00910094T AT E240008 T1 ATE240008 T1 AT E240008T1
Authority
AT
Austria
Prior art keywords
boards
interconnect
logic
emulation system
basic embodiment
Prior art date
Application number
AT00910094T
Other languages
English (en)
Inventor
Frederic Reblewski
Jean Barbier
Olivier Lepape
Original Assignee
Mentor Graphics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mentor Graphics Corp filed Critical Mentor Graphics Corp
Application granted granted Critical
Publication of ATE240008T1 publication Critical patent/ATE240008T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Image Processing (AREA)
  • Medicines Containing Antibodies Or Antigens For Use As Internal Diagnostic Agents (AREA)
AT00910094T 1999-09-24 2000-02-04 Skalierung eines emulation-systems ATE240008T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/405,602 US6647362B1 (en) 1999-09-24 1999-09-24 Emulation system scaling
PCT/US2000/003111 WO2001024369A1 (en) 1999-09-24 2000-02-04 Emulation system scaling

Publications (1)

Publication Number Publication Date
ATE240008T1 true ATE240008T1 (de) 2003-05-15

Family

ID=23604375

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00910094T ATE240008T1 (de) 1999-09-24 2000-02-04 Skalierung eines emulation-systems

Country Status (7)

Country Link
US (1) US6647362B1 (de)
EP (1) EP1114513B1 (de)
JP (1) JP3594557B2 (de)
AT (1) ATE240008T1 (de)
AU (1) AU3224200A (de)
DE (1) DE60002550T2 (de)
WO (1) WO2001024369A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030229612A1 (en) * 2002-06-10 2003-12-11 Keller S. Brandon Circuit design duplication system
WO2005055563A2 (en) 2003-11-28 2005-06-16 Warburton Kenneth J Bridged parallel distributing frame
US7698118B2 (en) * 2004-04-15 2010-04-13 Mentor Graphics Corporation Logic design modeling and interconnection
US7379861B2 (en) * 2004-05-28 2008-05-27 Quickturn Design Systems, Inc. Dynamic programming of trigger conditions in hardware emulation systems
TWI450118B (zh) * 2010-11-02 2014-08-21 Global Unichip Corp 混合的電子設計系統及其可重組連接矩陣
EP3416856A4 (de) 2016-02-16 2019-10-09 Developpement Effenco Inc. Stopp-start-kraftstoffsparendes system mit erweiterter funktionalität für berufsfahrzeuge

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4914612A (en) 1988-03-31 1990-04-03 International Business Machines Corporation Massively distributed simulation engine
JP3060018B2 (ja) 1988-10-05 2000-07-04 クイックターン デザイン システムズ インコーポレイテッド 複数の電気的に再構成可能なゲートアレイを用いて論理構成を構築する方法
US5282271A (en) 1991-10-30 1994-01-25 I-Cube Design Systems, Inc. I/O buffering system to a programmable switching apparatus
US5352123A (en) 1992-06-08 1994-10-04 Quickturn Systems, Incorporated Switching midplane and interconnection system for interconnecting large numbers of signals
US5424589A (en) 1993-02-12 1995-06-13 The Board Of Trustees Of The Leland Stanford Junior University Electrically programmable inter-chip interconnect architecture
US5682107A (en) 1994-04-01 1997-10-28 Xilinx, Inc. FPGA architecture with repeatable tiles including routing matrices and logic matrices
US5604888A (en) 1994-04-07 1997-02-18 Zycad Corporation Emulation system employing motherboard and flexible daughterboards
US5838908A (en) * 1994-11-14 1998-11-17 Texas Instruments Incorporated Device for having processors each having interface for transferring delivery units specifying direction and distance and operable to emulate plurality of field programmable gate arrays
US5907697A (en) 1995-10-13 1999-05-25 Mentor Graphics Corporation Emulation system having a scalable multi-level multi-stage hybrid programmable interconnect network
US5574388A (en) 1995-10-13 1996-11-12 Mentor Graphics Corporation Emulation system having a scalable multi-level multi-stage programmable interconnect network
US5903744A (en) 1997-05-15 1999-05-11 Logic Express System, Inc. Logic emulator using a disposable wire-wrap interconnect board with an FPGA emulation board

Also Published As

Publication number Publication date
DE60002550T2 (de) 2004-03-18
JP3594557B2 (ja) 2004-12-02
EP1114513A1 (de) 2001-07-11
JP2002538539A (ja) 2002-11-12
AU3224200A (en) 2001-04-30
DE60002550D1 (de) 2003-06-12
EP1114513B1 (de) 2003-05-07
WO2001024369A1 (en) 2001-04-05
US6647362B1 (en) 2003-11-11

Similar Documents

Publication Publication Date Title
DE69808286D1 (de) Emulationssytem mit zeitmultiplexverbindung
Zhang et al. A 1 V heterogeneous reconfigurable processor IC for baseband wireless applications
ATE278986T1 (de) Verteilter logik-analysator für ein hardware- logikemulationssystem
TW333696B (en) Memory module
WO2002021693A3 (en) Field programmable gate array and microcontroller system-on-a-chip
WO2008063251A3 (en) Memory circuit system and method
WO2001084170A3 (en) Source synchronous link integrity validation
ATE264510T1 (de) Umkonfigurierbare integrierte schaltung mit eingebautem fehlersuchsystem für ein simulationssystem
FI950970L (fi) Renkaan muotoisia piirikomponentteja, jotka on kytketty piirilevyn läpimenoreikään
WO2006042041A3 (en) High density midplane
ATE240008T1 (de) Skalierung eines emulation-systems
WO2003032492A3 (en) A reconfigurable integrated circuit with a scalable architecture
PL1648256T3 (pl) Sprzączka do czasowego łączenia kilku pasków
WO2002086723A3 (en) Emulator with switching network connections
DK1664548T3 (da) Modulsystem
ES2193041T3 (es) Dispositivo de reproduccion funcional de un circuito integrado especifico y su utilizacion como dispositivo de emulacion.
CN206022836U (zh) 一种信号转接板
WO2001031516A3 (en) An emulation system having a efficient emulation signal routing architecture
TW200723301A (en) Semiconductor memory card
DE60236270D1 (de) Vorrichtung zum verbinden von übertragungswegen
Necula Modeling And Simulation Of An ATM Switch.
JPS5611557A (en) Board computer unit
WO2002041167A3 (en) Method and apparatus for dynamically testing electrical interconnect
BR0007384A (pt) Chave múltipla integral
SE9903368D0 (sv) Kopplingsanordning för en anslutningsenhet

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties