ATE240553T1 - Einrichtung und verfahren zum einschalten einer funktion in einem vielspeichermodul - Google Patents

Einrichtung und verfahren zum einschalten einer funktion in einem vielspeichermodul

Info

Publication number
ATE240553T1
ATE240553T1 AT96944435T AT96944435T ATE240553T1 AT E240553 T1 ATE240553 T1 AT E240553T1 AT 96944435 T AT96944435 T AT 96944435T AT 96944435 T AT96944435 T AT 96944435T AT E240553 T1 ATE240553 T1 AT E240553T1
Authority
AT
Austria
Prior art keywords
circuit
memory
enabling
accessing
circuits
Prior art date
Application number
AT96944435T
Other languages
English (en)
Inventor
Gary R Gilliam
Kevin G Duesman
Leland R Nevill
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE240553T1 publication Critical patent/ATE240553T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Transceivers (AREA)
AT96944435T 1995-12-22 1996-12-19 Einrichtung und verfahren zum einschalten einer funktion in einem vielspeichermodul ATE240553T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/577,840 US5825697A (en) 1995-12-22 1995-12-22 Circuit and method for enabling a function in a multiple memory device module
PCT/US1996/020113 WO1997025674A1 (en) 1995-12-22 1996-12-19 Circuit and method for enabling a function in a multiple memory device module

Publications (1)

Publication Number Publication Date
ATE240553T1 true ATE240553T1 (de) 2003-05-15

Family

ID=24310366

Family Applications (1)

Application Number Title Priority Date Filing Date
AT96944435T ATE240553T1 (de) 1995-12-22 1996-12-19 Einrichtung und verfahren zum einschalten einer funktion in einem vielspeichermodul

Country Status (8)

Country Link
US (2) US5825697A (de)
EP (1) EP0868693B1 (de)
JP (1) JP4009686B2 (de)
KR (1) KR100441817B1 (de)
AT (1) ATE240553T1 (de)
AU (1) AU1424297A (de)
DE (1) DE69628196T2 (de)
WO (1) WO1997025674A1 (de)

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KR100504433B1 (ko) * 1999-01-09 2005-07-29 주식회사 하이닉스반도체 앤티퓨즈를 이용한 메모리소자의 리페어 회로
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US7313740B2 (en) * 2002-07-25 2007-12-25 Inapac Technology, Inc. Internally generating patterns for testing in an integrated circuit device
US7404117B2 (en) * 2005-10-24 2008-07-22 Inapac Technology, Inc. Component testing and recovery
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US8286046B2 (en) 2001-09-28 2012-10-09 Rambus Inc. Integrated circuit testing module including signal shaping interface
US7245141B2 (en) 2002-11-27 2007-07-17 Inapac Technology, Inc. Shared bond pad for testing a memory within a packaged semiconductor device
US8166361B2 (en) 2001-09-28 2012-04-24 Rambus Inc. Integrated circuit testing module configured for set-up and hold time testing
US20040019841A1 (en) * 2002-07-25 2004-01-29 Ong Adrian E. Internally generating patterns for testing in an integrated circuit device
US7061263B1 (en) 2001-11-15 2006-06-13 Inapac Technology, Inc. Layout and use of bond pads and probe pads for testing of integrated circuits devices
US7466160B2 (en) * 2002-11-27 2008-12-16 Inapac Technology, Inc. Shared memory bus architecture for system with processor and memory units
US8063650B2 (en) 2002-11-27 2011-11-22 Rambus Inc. Testing fuse configurations in semiconductor devices
US7673193B1 (en) * 2005-08-18 2010-03-02 Rambus Inc. Processor-memory unit for use in system-in-package and system-in-module devices
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US7006393B2 (en) * 2004-06-07 2006-02-28 Micron Technology, Inc. Method and apparatus for semiconductor device repair with reduced number of programmable elements
US7218561B2 (en) * 2004-06-07 2007-05-15 Micron Technology, Inc. Apparatus and method for semiconductor device repair with reduced number of programmable elements
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
JP5242397B2 (ja) 2005-09-02 2013-07-24 メタラム インコーポレイテッド Ｄｒａｍをスタックする方法及び装置
US7779311B2 (en) * 2005-10-24 2010-08-17 Rambus Inc. Testing and recovery in a multilayer device
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
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US7385861B1 (en) * 2006-08-18 2008-06-10 Ambarella, Inc. Synchronization circuit for DDR IO interface
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JP5726080B2 (ja) * 2008-09-30 2015-05-27 ドイッチェ テレコム アーゲー 非接触型インターフェース装置を権限に応じて制御する方法および通信システム
EP2441007A1 (de) 2009-06-09 2012-04-18 Google, Inc. Programmierung von dimm-abschlusswiderstandswerten
US9256493B2 (en) * 2011-12-28 2016-02-09 Intel Corporation Memory module architecture
US10761588B2 (en) * 2018-08-09 2020-09-01 Micron Technology, Inc. Power configuration component including selectable configuration profiles corresponding to operating characteristics of the power configuration component
US11670379B2 (en) * 2020-12-04 2023-06-06 Micron Technology, Inc. Sense line structures in capacitive sense NAND memory

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Also Published As

Publication number Publication date
US5920516A (en) 1999-07-06
EP0868693B1 (de) 2003-05-14
JP4009686B2 (ja) 2007-11-21
KR19990076659A (ko) 1999-10-15
DE69628196D1 (de) 2003-06-18
AU1424297A (en) 1997-08-01
KR100441817B1 (ko) 2004-10-12
JP2000503152A (ja) 2000-03-14
WO1997025674A1 (en) 1997-07-17
EP0868693A1 (de) 1998-10-07
US5825697A (en) 1998-10-20
DE69628196T2 (de) 2004-04-01

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