ATE240619T1 - Vorrichtung und verfahren zur schnellen paketvermittlung - Google Patents
Vorrichtung und verfahren zur schnellen paketvermittlungInfo
- Publication number
- ATE240619T1 ATE240619T1 AT91908488T AT91908488T ATE240619T1 AT E240619 T1 ATE240619 T1 AT E240619T1 AT 91908488 T AT91908488 T AT 91908488T AT 91908488 T AT91908488 T AT 91908488T AT E240619 T1 ATE240619 T1 AT E240619T1
- Authority
- AT
- Austria
- Prior art keywords
- packet
- nodes
- packets
- memory elements
- transmit
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/004—Error avoidance
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
- G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30047—Prefetch instructions; cache control instructions
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/468—Specific access rights for resources, e.g. using capability register
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4637—Interconnected ring systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/02—Topology update or discovery
- H04L45/04—Interdomain routing, e.g. hierarchical routing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
- H04L49/105—ATM switching elements
- H04L49/107—ATM switching elements using shared medium
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
- H04L49/309—Header conversion, routing tables or routing tags
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/27—Using a specific cache architecture
- G06F2212/272—Cache only memory architecture [COMA]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/5681—Buffer or queue management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Quality & Reliability (AREA)
- Multimedia (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Auxiliary Devices For And Details Of Packaging Control (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/499,182 US5335325A (en) | 1987-12-22 | 1990-03-26 | High-speed packet switching apparatus and method |
| PCT/US1991/002004 WO1991015088A1 (en) | 1990-03-26 | 1991-03-25 | High-speed packet switching apparatus and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE240619T1 true ATE240619T1 (de) | 2003-05-15 |
Family
ID=23984179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT91908488T ATE240619T1 (de) | 1990-03-26 | 1991-03-25 | Vorrichtung und verfahren zur schnellen paketvermittlung |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5335325A (de) |
| EP (1) | EP0473777B1 (de) |
| JP (1) | JP3428640B2 (de) |
| AT (1) | ATE240619T1 (de) |
| DE (1) | DE69133257T2 (de) |
| WO (1) | WO1991015088A1 (de) |
Families Citing this family (44)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6067408A (en) * | 1993-05-27 | 2000-05-23 | Advanced Micro Devices, Inc. | Full duplex buffer management and apparatus |
| CA2135681C (en) * | 1993-12-30 | 2000-01-18 | Srinivas V. Makam | System and method for directly accessing long-term memory devices |
| EP0685949A3 (de) * | 1994-06-03 | 2002-07-10 | Philips Patentverwaltung GmbH | Paketübermittlungssystem |
| US5717895A (en) * | 1994-12-01 | 1998-02-10 | Cray Research, Inc. | Associative scalar data cache with write-through capabilities for a vector processor |
| US5619497A (en) * | 1994-12-22 | 1997-04-08 | Emc Corporation | Method and apparatus for reordering frames |
| US5752264A (en) * | 1995-03-31 | 1998-05-12 | International Business Machines Corporation | Computer architecture incorporating processor clusters and hierarchical cache memories |
| US5592622A (en) * | 1995-05-10 | 1997-01-07 | 3Com Corporation | Network intermediate system with message passing architecture |
| US5802278A (en) * | 1995-05-10 | 1998-09-01 | 3Com Corporation | Bridge/router architecture for high performance scalable networking |
| US5870538A (en) | 1995-07-19 | 1999-02-09 | Fujitsu Network Communications, Inc. | Switch fabric controller comparator system and method |
| US6728959B1 (en) | 1995-08-08 | 2004-04-27 | Novell, Inc. | Method and apparatus for strong affinity multiprocessor scheduling |
| WO1997010656A1 (en) | 1995-09-14 | 1997-03-20 | Fujitsu Network Communications, Inc. | Transmitter controlled flow control for buffer allocation in wide area atm networks |
| SE516763C2 (sv) * | 1995-10-20 | 2002-02-26 | Ericsson Telefon Ab L M | Förfarande och system för signalutbyte med ett kommunikationsnät |
| JP2000517488A (ja) | 1996-01-16 | 2000-12-26 | フジツウ ネットワーク コミュニケーションズ,インコーポレイテッド | Atm網用の信頼性と柔軟性のあるマルチキャスト機構 |
| US6374329B1 (en) | 1996-02-20 | 2002-04-16 | Intergraph Corporation | High-availability super server |
| US5748905A (en) | 1996-08-30 | 1998-05-05 | Fujitsu Network Communications, Inc. | Frame classification using classification keys |
| US20060129627A1 (en) * | 1996-11-22 | 2006-06-15 | Mangosoft Corp. | Internet-based shared file service with native PC client access and semantics and distributed version control |
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| US6026474A (en) * | 1996-11-22 | 2000-02-15 | Mangosoft Corporation | Shared client-side web caching using globally addressable memory |
| US7058696B1 (en) | 1996-11-22 | 2006-06-06 | Mangosoft Corporation | Internet-based shared file service with native PC client access and semantics |
| US6148377A (en) * | 1996-11-22 | 2000-11-14 | Mangosoft Corporation | Shared memory computer networks |
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| US6647393B1 (en) | 1996-11-22 | 2003-11-11 | Mangosoft Corporation | Dynamic directory service |
| US7100020B1 (en) * | 1998-05-08 | 2006-08-29 | Freescale Semiconductor, Inc. | Digital communications processor |
| US6138113A (en) * | 1998-08-10 | 2000-10-24 | Altavista Company | Method for identifying near duplicate pages in a hyperlinked database |
| US7013354B1 (en) * | 1998-10-05 | 2006-03-14 | Canon Kabushiki Kaisha | Channel protocol for IEEE 1394 data transmission |
| US6310881B1 (en) | 1998-10-20 | 2001-10-30 | Terabeam Corporation | Method and apparatus for network control |
| JP4237865B2 (ja) * | 1999-04-27 | 2009-03-11 | 富士通マイクロエレクトロニクス株式会社 | パケット転送制御装置及びその方法 |
| CA2271539A1 (en) * | 1999-05-12 | 2000-11-12 | Pmc-Sierra Inc. | Interface between a link layer device and one or more physical layer devices |
| JP3643507B2 (ja) * | 1999-09-20 | 2005-04-27 | 株式会社東芝 | パケット処理装置及びパケット処理方法 |
| US6775757B1 (en) * | 1999-12-14 | 2004-08-10 | Genesis Microchip Inc. | Multi-component processor |
| US6742083B1 (en) | 1999-12-14 | 2004-05-25 | Genesis Microchip Inc. | Method and apparatus for multi-part processing of program code by a single processor |
| US6920543B1 (en) * | 1999-12-14 | 2005-07-19 | Genesis Microchip, Inc. | Method and apparatus for performing distributed processing of program code |
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| EP0214718A3 (de) * | 1985-07-22 | 1990-04-04 | Alliant Computer Systems Corporation | Digitalrechner |
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| JPS6336348A (ja) * | 1986-07-30 | 1988-02-17 | Toshiba Corp | バツフアメモリ管理方法 |
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-
1990
- 1990-03-26 US US07/499,182 patent/US5335325A/en not_active Expired - Lifetime
-
1991
- 1991-03-25 JP JP50759691A patent/JP3428640B2/ja not_active Expired - Fee Related
- 1991-03-25 WO PCT/US1991/002004 patent/WO1991015088A1/en not_active Ceased
- 1991-03-25 EP EP91908488A patent/EP0473777B1/de not_active Expired - Lifetime
- 1991-03-25 AT AT91908488T patent/ATE240619T1/de not_active IP Right Cessation
- 1991-03-25 DE DE69133257T patent/DE69133257T2/de not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3428640B2 (ja) | 2003-07-22 |
| WO1991015088A1 (en) | 1991-10-03 |
| EP0473777A1 (de) | 1992-03-11 |
| EP0473777A4 (en) | 1995-02-01 |
| EP0473777B1 (de) | 2003-05-14 |
| DE69133257D1 (de) | 2003-06-18 |
| JPH05501041A (ja) | 1993-02-25 |
| US5335325A (en) | 1994-08-02 |
| DE69133257T2 (de) | 2004-04-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |