ATE243894T1 - Halteschaltung in dominologic mit rückstellzeit - Google Patents

Halteschaltung in dominologic mit rückstellzeit

Info

Publication number
ATE243894T1
ATE243894T1 AT00308322T AT00308322T ATE243894T1 AT E243894 T1 ATE243894 T1 AT E243894T1 AT 00308322 T AT00308322 T AT 00308322T AT 00308322 T AT00308322 T AT 00308322T AT E243894 T1 ATE243894 T1 AT E243894T1
Authority
AT
Austria
Prior art keywords
phase
logic circuit
domino logic
precharge
evaluate
Prior art date
Application number
AT00308322T
Other languages
English (en)
Inventor
Patrick W Bosshart
Paul E Landman
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of ATE243894T1 publication Critical patent/ATE243894T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
AT00308322T 1999-09-24 2000-09-22 Halteschaltung in dominologic mit rückstellzeit ATE243894T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/405,688 US6242952B1 (en) 1999-09-24 1999-09-24 Inverting hold time latch circuits, systems, and methods

Publications (1)

Publication Number Publication Date
ATE243894T1 true ATE243894T1 (de) 2003-07-15

Family

ID=23604788

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00308322T ATE243894T1 (de) 1999-09-24 2000-09-22 Halteschaltung in dominologic mit rückstellzeit

Country Status (5)

Country Link
US (1) US6242952B1 (de)
EP (1) EP1087529B1 (de)
JP (1) JP2001144605A (de)
AT (1) ATE243894T1 (de)
DE (1) DE60003503T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7009427B1 (en) * 2000-07-11 2006-03-07 Piconetics, Inc. Low power dynamic inverter logic gate with inverter-like output
US6459316B1 (en) 2000-12-08 2002-10-01 Intel Corporation Flip flop circuit
US6701339B2 (en) 2000-12-08 2004-03-02 Intel Corporation Pipelined compressor circuit
US6779013B2 (en) * 2001-06-04 2004-08-17 Intel Corporation Floating point overflow and sign detection
US20030154227A1 (en) * 2002-02-08 2003-08-14 Intel Corporation Multi-threaded multiply accumulator
US6978387B2 (en) * 2002-11-29 2005-12-20 Texas Instruments Incorporated Hold time latch with decreased percharge node voltage leakage
US6937079B1 (en) 2003-07-28 2005-08-30 University Of Louisiana At Lafayette Single-transistor-clocked flip-flop
US7282960B2 (en) * 2005-06-28 2007-10-16 International Business Machines Corporation Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock
US7411425B2 (en) * 2005-06-28 2008-08-12 International Business Machines Corporation Method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit
US7505326B2 (en) 2006-10-31 2009-03-17 Atmel Corporation Programming pulse generator
US7417904B2 (en) 2006-10-31 2008-08-26 Atmel Corporation Adaptive gate voltage regulation
CN114141199B (zh) * 2021-12-03 2024-03-15 湖畔光电科技（江苏）有限公司 微显示无源像素电路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4841174A (en) * 1985-10-21 1989-06-20 Western Digital Corporation CMOS circuit with racefree single clock dynamic logic
US5831451A (en) * 1996-07-19 1998-11-03 Texas Instruments Incorporated Dynamic logic circuits using transistors having differing threshold voltages
US5892372A (en) * 1997-01-27 1999-04-06 International Business Machines Corporation Creating inversions in ripple domino logic
US6040716A (en) * 1997-05-19 2000-03-21 Texas Instruments Incorporated Domino logic circuits, systems, and methods with precharge control based on completion of evaluation by the subsequent domino logic stage
US6049231A (en) * 1997-07-21 2000-04-11 Texas Instruments Incorporated Dynamic multiplexer circuits, systems, and methods having three signal inversions from input to output
US5942917A (en) * 1997-12-29 1999-08-24 Intel Corporation High speed ratioed CMOS logic structures for a pulsed input environment

Also Published As

Publication number Publication date
EP1087529A3 (de) 2001-04-04
DE60003503D1 (de) 2003-07-31
JP2001144605A (ja) 2001-05-25
EP1087529A2 (de) 2001-03-28
EP1087529B1 (de) 2003-06-25
US6242952B1 (en) 2001-06-05
DE60003503T2 (de) 2004-04-29

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties