ATE266881T1 - Ein schnittstellengerät zum verbinden von geräten mit verschiedenen taktfrequenzen und verfahren zum betreiben der schnittstelle - Google Patents

Ein schnittstellengerät zum verbinden von geräten mit verschiedenen taktfrequenzen und verfahren zum betreiben der schnittstelle

Info

Publication number
ATE266881T1
ATE266881T1 AT98932159T AT98932159T ATE266881T1 AT E266881 T1 ATE266881 T1 AT E266881T1 AT 98932159 T AT98932159 T AT 98932159T AT 98932159 T AT98932159 T AT 98932159T AT E266881 T1 ATE266881 T1 AT E266881T1
Authority
AT
Austria
Prior art keywords
data
buffer registers
signal
data transfer
reg2
Prior art date
Application number
AT98932159T
Other languages
English (en)
Inventor
Aki Happonen
Original Assignee
Nokia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Corp filed Critical Nokia Corp
Application granted granted Critical
Publication of ATE266881T1 publication Critical patent/ATE266881T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
AT98932159T 1998-06-17 1998-06-17 Ein schnittstellengerät zum verbinden von geräten mit verschiedenen taktfrequenzen und verfahren zum betreiben der schnittstelle ATE266881T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP1998/003642 WO1999066392A1 (en) 1998-06-17 1998-06-17 An interface apparatus for connecting devices operating at different clock rates, and a method of operating the interface

Publications (1)

Publication Number Publication Date
ATE266881T1 true ATE266881T1 (de) 2004-05-15

Family

ID=8166977

Family Applications (1)

Application Number Title Priority Date Filing Date
AT98932159T ATE266881T1 (de) 1998-06-17 1998-06-17 Ein schnittstellengerät zum verbinden von geräten mit verschiedenen taktfrequenzen und verfahren zum betreiben der schnittstelle

Country Status (9)

Country Link
US (1) US6754740B2 (de)
EP (1) EP1086416B1 (de)
JP (1) JP2002518729A (de)
CN (1) CN1295685A (de)
AT (1) ATE266881T1 (de)
AU (1) AU756039B2 (de)
DE (1) DE69823885T2 (de)
NO (1) NO20006400L (de)
WO (1) WO1999066392A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6789153B1 (en) * 2001-02-20 2004-09-07 Lsi Logic Corporation Bridge for coupling digital signal processor to on-chip bus as slave
US6907480B2 (en) 2001-07-11 2005-06-14 Seiko Epson Corporation Data processing apparatus and data input/output apparatus and data input/output method
JP2003067324A (ja) * 2001-08-29 2003-03-07 Oki Electric Ind Co Ltd インタフェース回路
EP1430669B1 (de) * 2001-09-26 2005-05-11 Siemens Aktiengesellschaft Verfahren zur verarbeitung konsistenter datensätze
DE10152195A1 (de) * 2001-10-23 2003-04-30 Koninkl Philips Electronics Nv Schaltungsanordnung
JP4547198B2 (ja) * 2004-06-30 2010-09-22 富士通株式会社 演算装置、演算装置の制御方法、プログラム及びコンピュータ読取り可能記録媒体
JP4525726B2 (ja) * 2007-10-23 2010-08-18 富士ゼロックス株式会社 復号装置、復号プログラム及び画像処理装置
JP2011028343A (ja) * 2009-07-22 2011-02-10 Fujitsu Ltd 演算処理装置、およびデータ転送方法
CN101923524B (zh) * 2010-08-04 2012-08-22 苏州国芯科技有限公司 一种基于clb总线的存储器接口方法
CN104247306B (zh) * 2012-08-28 2017-06-06 华为技术有限公司 光接收器
CN111488297B (zh) * 2020-04-02 2023-04-14 杭州迪普科技股份有限公司 用于访问寄存器的方法、装置、电子设备及可读介质
CN114895612B (zh) * 2022-07-11 2022-09-27 深圳市杰美康机电有限公司 一种用于dsp芯片的仿真系统

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4298954A (en) * 1979-04-30 1981-11-03 International Business Machines Corporation Alternating data buffers when one buffer is empty and another buffer is variably full of data
FR2623349A1 (fr) * 1987-11-18 1989-05-19 Alcatel Thomson Faisceaux Dispositif de retard d'au moins un train de donnees binaires a haut debit
US4888741A (en) * 1988-12-27 1989-12-19 Harris Corporation Memory with cache register interface structure
JP2572292B2 (ja) * 1990-05-14 1997-01-16 株式会社小松製作所 非同期データ伝送装置
US5371877A (en) * 1991-12-31 1994-12-06 Apple Computer, Inc. Apparatus for alternatively accessing single port random access memories to implement dual port first-in first-out memory
GB2282472B (en) 1993-10-01 1998-07-15 Nokia Mobile Phones Ltd An interface between unsynchronised devices
FI104858B (fi) 1995-05-29 2000-04-14 Nokia Networks Oy Menetelmä ja laitteisto asynkronisen väylän sovittamiseksi synkroniseen piiriin
US6130891A (en) * 1997-02-14 2000-10-10 Advanced Micro Devices, Inc. Integrated multiport switch having management information base (MIB) interface temporary storage
FI105727B (fi) 1997-05-15 2000-09-29 Nokia Networks Oy Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin
US6055285A (en) * 1997-11-17 2000-04-25 Qlogic Corporation Synchronization circuit for transferring pointer between two asynchronous circuits
US6033441A (en) * 1997-12-23 2000-03-07 Lsi Logic Corporation Method and apparatus for synchronizing data transfer
US6473818B1 (en) * 1998-09-09 2002-10-29 Advanced Micro Devices, Inc. Apparatus and method in a network interface device for asynchronously generating SRAM full and empty flags using coded read and write pointer values

Also Published As

Publication number Publication date
DE69823885D1 (de) 2004-06-17
EP1086416B1 (de) 2004-05-12
NO20006400L (no) 2001-02-15
EP1086416A1 (de) 2001-03-28
US20010016885A1 (en) 2001-08-23
DE69823885T2 (de) 2005-04-21
NO20006400D0 (no) 2000-12-15
AU756039B2 (en) 2003-01-02
CN1295685A (zh) 2001-05-16
JP2002518729A (ja) 2002-06-25
AU8215898A (en) 2000-01-05
WO1999066392A1 (en) 1999-12-23
US6754740B2 (en) 2004-06-22

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