NO20006400D0 - Grensesnittapparat for å gi forbindelse mellom anordninger som fungerer ved forskjellige klokkefrekvenser, samt fremgangsmåte for drift av grensesnittet - Google Patents

Grensesnittapparat for å gi forbindelse mellom anordninger som fungerer ved forskjellige klokkefrekvenser, samt fremgangsmåte for drift av grensesnittet

Info

Publication number
NO20006400D0
NO20006400D0 NO20006400A NO20006400A NO20006400D0 NO 20006400 D0 NO20006400 D0 NO 20006400D0 NO 20006400 A NO20006400 A NO 20006400A NO 20006400 A NO20006400 A NO 20006400A NO 20006400 D0 NO20006400 D0 NO 20006400D0
Authority
NO
Norway
Prior art keywords
data
buffer registers
signal
data transfer
operating
Prior art date
Application number
NO20006400A
Other languages
English (en)
Other versions
NO20006400L (no
Inventor
Aki Happonen
Original Assignee
Nokia Networks Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Networks Oy filed Critical Nokia Networks Oy
Publication of NO20006400D0 publication Critical patent/NO20006400D0/no
Publication of NO20006400L publication Critical patent/NO20006400L/no

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
NO20006400A 1998-06-17 2000-12-15 Grensesnittapparat for å gi forbindelse mellom anordninger som fungerer ved forskjellige klokkefrekvenser, samt fremgangsmåte for drift av grensesnittet NO20006400L (no)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP1998/003642 WO1999066392A1 (en) 1998-06-17 1998-06-17 An interface apparatus for connecting devices operating at different clock rates, and a method of operating the interface

Publications (2)

Publication Number Publication Date
NO20006400D0 true NO20006400D0 (no) 2000-12-15
NO20006400L NO20006400L (no) 2001-02-15

Family

ID=8166977

Family Applications (1)

Application Number Title Priority Date Filing Date
NO20006400A NO20006400L (no) 1998-06-17 2000-12-15 Grensesnittapparat for å gi forbindelse mellom anordninger som fungerer ved forskjellige klokkefrekvenser, samt fremgangsmåte for drift av grensesnittet

Country Status (9)

Country Link
US (1) US6754740B2 (no)
EP (1) EP1086416B1 (no)
JP (1) JP2002518729A (no)
CN (1) CN1295685A (no)
AT (1) ATE266881T1 (no)
AU (1) AU756039B2 (no)
DE (1) DE69823885T2 (no)
NO (1) NO20006400L (no)
WO (1) WO1999066392A1 (no)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6789153B1 (en) * 2001-02-20 2004-09-07 Lsi Logic Corporation Bridge for coupling digital signal processor to on-chip bus as slave
US6907480B2 (en) 2001-07-11 2005-06-14 Seiko Epson Corporation Data processing apparatus and data input/output apparatus and data input/output method
JP2003067324A (ja) * 2001-08-29 2003-03-07 Oki Electric Ind Co Ltd インタフェース回路
ATE295648T1 (de) * 2001-09-26 2005-05-15 Siemens Ag Verfahren zur verarbeitung konsistenter datensätze
DE10152195A1 (de) * 2001-10-23 2003-04-30 Koninkl Philips Electronics Nv Schaltungsanordnung
JP4547198B2 (ja) * 2004-06-30 2010-09-22 富士通株式会社 演算装置、演算装置の制御方法、プログラム及びコンピュータ読取り可能記録媒体
JP4525726B2 (ja) * 2007-10-23 2010-08-18 富士ゼロックス株式会社 復号装置、復号プログラム及び画像処理装置
JP2011028343A (ja) * 2009-07-22 2011-02-10 Fujitsu Ltd 演算処理装置、およびデータ転送方法
CN101923524B (zh) * 2010-08-04 2012-08-22 苏州国芯科技有限公司 一种基于clb总线的存储器接口方法
CN104247306B (zh) * 2012-08-28 2017-06-06 华为技术有限公司 光接收器
CN111488297B (zh) * 2020-04-02 2023-04-14 杭州迪普科技股份有限公司 用于访问寄存器的方法、装置、电子设备及可读介质
CN114895612B (zh) * 2022-07-11 2022-09-27 深圳市杰美康机电有限公司 一种用于dsp芯片的仿真系统

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4298954A (en) * 1979-04-30 1981-11-03 International Business Machines Corporation Alternating data buffers when one buffer is empty and another buffer is variably full of data
FR2623349A1 (fr) * 1987-11-18 1989-05-19 Alcatel Thomson Faisceaux Dispositif de retard d'au moins un train de donnees binaires a haut debit
US4888741A (en) * 1988-12-27 1989-12-19 Harris Corporation Memory with cache register interface structure
JP2572292B2 (ja) * 1990-05-14 1997-01-16 株式会社小松製作所 非同期データ伝送装置
US5371877A (en) * 1991-12-31 1994-12-06 Apple Computer, Inc. Apparatus for alternatively accessing single port random access memories to implement dual port first-in first-out memory
GB2282472B (en) 1993-10-01 1998-07-15 Nokia Mobile Phones Ltd An interface between unsynchronised devices
FI104858B (fi) 1995-05-29 2000-04-14 Nokia Networks Oy Menetelmä ja laitteisto asynkronisen väylän sovittamiseksi synkroniseen piiriin
US6130891A (en) * 1997-02-14 2000-10-10 Advanced Micro Devices, Inc. Integrated multiport switch having management information base (MIB) interface temporary storage
FI105727B (fi) 1997-05-15 2000-09-29 Nokia Networks Oy Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin
US6055285A (en) * 1997-11-17 2000-04-25 Qlogic Corporation Synchronization circuit for transferring pointer between two asynchronous circuits
US6033441A (en) * 1997-12-23 2000-03-07 Lsi Logic Corporation Method and apparatus for synchronizing data transfer
US6473818B1 (en) * 1998-09-09 2002-10-29 Advanced Micro Devices, Inc. Apparatus and method in a network interface device for asynchronously generating SRAM full and empty flags using coded read and write pointer values

Also Published As

Publication number Publication date
WO1999066392A1 (en) 1999-12-23
US20010016885A1 (en) 2001-08-23
ATE266881T1 (de) 2004-05-15
AU756039B2 (en) 2003-01-02
US6754740B2 (en) 2004-06-22
JP2002518729A (ja) 2002-06-25
EP1086416B1 (en) 2004-05-12
NO20006400L (no) 2001-02-15
AU8215898A (en) 2000-01-05
EP1086416A1 (en) 2001-03-28
DE69823885T2 (de) 2005-04-21
CN1295685A (zh) 2001-05-16
DE69823885D1 (de) 2004-06-17

Similar Documents

Publication Publication Date Title
KR100494201B1 (ko) 메모리시스템,i/o서브시스템장치,및메모리장치를동작시키는방법
EP1652058B1 (en) Switch/network adapter port incorporating selectively accessible shared memory resources
JP5261803B2 (ja) 不揮発性メモリ用の高速ファンアウトシステムアーキテクチャおよび入出力回路
NO20006400D0 (no) Grensesnittapparat for å gi forbindelse mellom anordninger som fungerer ved forskjellige klokkefrekvenser, samt fremgangsmåte for drift av grensesnittet
KR960704274A (ko) 데이터 스트림 모드를 스위칭할 수 있는 메모리 장치(memory device with switching of date stream modes)
KR940012147A (ko) 마이크로컴퓨터 시스템
DE3751426D1 (de) Busschnittstellenschaltung für digitalen Datenprozessor.
KR900008516A (ko) 버퍼 기억장치
KR100390058B1 (ko) 주국과적어도하나의종국을갖는통신시스템
US5944806A (en) Microprocessor with versatile addressing
JP2006228194A (ja) 内部メモリデバイス間の直接的データ移動が可能な複合メモリチップおよびデータ移動方法
US6138188A (en) Buffer management device and method for improving buffer usage and access performance in data processing system
WO1999026141A1 (en) Method and apparatus for controlling shared memory access
KR940007686A (ko) 캐시(Cache) 메모리를 가지는 프로세서(Processor)
JPH0642227B2 (ja) デ−タ転送装置
KR100606698B1 (ko) 인터페이스 장치
JPS593776B2 (ja) マルチマイクロプロセツサ・システムにおける交信方法
JPS6120167A (ja) デ−タ記憶装置
JPH0160864B2 (no)
KR970016898A (ko) 데이터 처리기 및 억세스 방법
KR100331557B1 (ko) 순차적 전송 기능을 갖는 출력단 및 이를 내장하는 반도체 메모리 장치를 구비하는 메모리 시스템
KR950009603A (ko) 고속 데이타 전송 시스템
KR970019223A (ko) 클럭주기가 다른 블럭들의 데이타 전송방법 및 회로
KR910003497A (ko) 내부 버스라인 수를 줄인 데이타 처리장치
KR19990031909A (ko) 데이터 제어방법

Legal Events

Date Code Title Description
FC2A Withdrawal, rejection or dismissal of laid open patent application