ATE292305T1 - System mit schnittstellen und einem schalter für die trennung von kohärentem und nichtkohärentem datenpaketverkehr - Google Patents

System mit schnittstellen und einem schalter für die trennung von kohärentem und nichtkohärentem datenpaketverkehr

Info

Publication number
ATE292305T1
ATE292305T1 AT02025684T AT02025684T ATE292305T1 AT E292305 T1 ATE292305 T1 AT E292305T1 AT 02025684 T AT02025684 T AT 02025684T AT 02025684 T AT02025684 T AT 02025684T AT E292305 T1 ATE292305 T1 AT E292305T1
Authority
AT
Austria
Prior art keywords
switch
coherent
memory
interface
interconnect
Prior art date
Application number
AT02025684T
Other languages
English (en)
Inventor
Barton J Sano
Joseph B Rowlands
James B Keller
Laurent R Moll
Koray Oner
Manu Gulati
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE292305T1 publication Critical patent/ATE292305T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9068—Intermediate storage in different physical parts of a node or terminal in the network interface card
    • H04L49/9073—Early interruption upon arrival of a fraction of a packet
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3009—Header conversion, routing tables or routing tags

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)
AT02025684T 2001-11-20 2002-11-20 System mit schnittstellen und einem schalter für die trennung von kohärentem und nichtkohärentem datenpaketverkehr ATE292305T1 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US33178901P 2001-11-20 2001-11-20
US34471301P 2001-12-24 2001-12-24
US34877702P 2002-01-14 2002-01-14
US34871702P 2002-01-14 2002-01-14
US38074002P 2002-05-15 2002-05-15
US10/270,029 US6748479B2 (en) 2001-11-20 2002-10-11 System having interfaces and switch that separates coherent and packet traffic

Publications (1)

Publication Number Publication Date
ATE292305T1 true ATE292305T1 (de) 2005-04-15

Family

ID=27559482

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02025684T ATE292305T1 (de) 2001-11-20 2002-11-20 System mit schnittstellen und einem schalter für die trennung von kohärentem und nichtkohärentem datenpaketverkehr

Country Status (4)

Country Link
US (3) US6748479B2 (de)
EP (1) EP1313023B1 (de)
AT (1) ATE292305T1 (de)
DE (1) DE60203469T2 (de)

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Also Published As

Publication number Publication date
US6941406B2 (en) 2005-09-06
EP1313023B1 (de) 2005-03-30
DE60203469T2 (de) 2006-02-23
US20040221072A1 (en) 2004-11-04
EP1313023A1 (de) 2003-05-21
US20050226234A1 (en) 2005-10-13
DE60203469D1 (de) 2005-05-04
US6748479B2 (en) 2004-06-08
US20030097416A1 (en) 2003-05-22

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