ATE295544T1 - Verfahren zur bereitstellung von bitweisen einschränkungen während einer test-generierung - Google Patents

Verfahren zur bereitstellung von bitweisen einschränkungen während einer test-generierung

Info

Publication number
ATE295544T1
ATE295544T1 AT01961108T AT01961108T ATE295544T1 AT E295544 T1 ATE295544 T1 AT E295544T1 AT 01961108 T AT01961108 T AT 01961108T AT 01961108 T AT01961108 T AT 01961108T AT E295544 T1 ATE295544 T1 AT E295544T1
Authority
AT
Austria
Prior art keywords
test generation
constraints
bitwise
language
providing
Prior art date
Application number
AT01961108T
Other languages
English (en)
Inventor
Vitaly Lagoon
Guy Barruch
Original Assignee
Verisity Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Verisity Ltd filed Critical Verisity Ltd
Application granted granted Critical
Publication of ATE295544T1 publication Critical patent/ATE295544T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Debugging And Monitoring (AREA)
  • Traffic Control Systems (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Investigating Or Analysing Biological Materials (AREA)
AT01961108T 2000-08-28 2001-08-28 Verfahren zur bereitstellung von bitweisen einschränkungen während einer test-generierung ATE295544T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22808700P 2000-08-28 2000-08-28
PCT/IL2001/000803 WO2002019108A2 (en) 2000-08-28 2001-08-28 Method for providing bitwise constraints for test generation

Publications (1)

Publication Number Publication Date
ATE295544T1 true ATE295544T1 (de) 2005-05-15

Family

ID=22855730

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01961108T ATE295544T1 (de) 2000-08-28 2001-08-28 Verfahren zur bereitstellung von bitweisen einschränkungen während einer test-generierung

Country Status (8)

Country Link
US (2) US6918076B2 (de)
EP (1) EP1314045B1 (de)
JP (1) JP4652663B2 (de)
AT (1) ATE295544T1 (de)
AU (1) AU2001282486A1 (de)
DE (1) DE60110811T2 (de)
IL (1) IL154585A0 (de)
WO (1) WO2002019108A2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002019108A2 (en) * 2000-08-28 2002-03-07 Verisity Ltd. Method for providing bitwise constraints for test generation
US7318014B1 (en) * 2002-05-31 2008-01-08 Altera Corporation Bit accurate hardware simulation in system level simulators
US7991606B1 (en) 2003-04-01 2011-08-02 Altera Corporation Embedded logic analyzer functionality for system level environments
US7509246B1 (en) 2003-06-09 2009-03-24 Altera Corporation System level simulation models for hardware modules
US7225416B1 (en) * 2004-06-15 2007-05-29 Altera Corporation Methods and apparatus for automatic test component generation and inclusion into simulation testbench
US7434101B2 (en) * 2005-03-21 2008-10-07 International Business Machines Corporation Highly specialized scenarios in random test generation
US7627843B2 (en) * 2005-03-23 2009-12-01 International Business Machines Corporation Dynamically interleaving randomly generated test-cases for functional verification
DE102005036321A1 (de) * 2005-07-29 2007-02-01 Siemens Ag Verfahren und Vorrichtung zum dynamischen Generieren von Testszenarien für komplexe rechnergesteuerte Systeme, z.B. für medizintechnische Anlagen
US20070113219A1 (en) * 2005-11-17 2007-05-17 Microsoft Corporation Representing simulation values of variable in sharpley limited time and space
US9218271B2 (en) * 2011-10-04 2015-12-22 International Business Machines Corporation Test planning based on dynamic coverage analysis
US9720792B2 (en) 2012-08-28 2017-08-01 Synopsys, Inc. Information theoretic caching for dynamic problem generation in constraint solving
US11468218B2 (en) 2012-08-28 2022-10-11 Synopsys, Inc. Information theoretic subgraph caching
US8904320B2 (en) 2013-03-13 2014-12-02 Synopsys, Inc. Solving multiplication constraints by factorization
US9298592B2 (en) 2013-03-14 2016-03-29 International Business Machines Corporation Testing a software interface for a streaming hardware device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2820701B2 (ja) * 1988-12-06 1998-11-05 三菱電機株式会社 ２進数への変換方法
JPH064330A (ja) * 1992-06-23 1994-01-14 Nec Corp 試験システム
GB9624935D0 (en) * 1996-11-29 1997-01-15 Sgs Thomson Microelectronics System and method for representing physical environment
US6182258B1 (en) 1997-06-03 2001-01-30 Verisity Ltd. Method and apparatus for test generation during circuit design
US5832418A (en) * 1997-06-23 1998-11-03 Micron Electronics Apparatus for testing a controller with random contraints
AU1962700A (en) * 1998-11-09 2000-05-29 Luk Lamellen Und Kupplungsbau Gmbh Motor vehicle
AU2001275508A1 (en) * 2000-06-02 2001-12-11 Joseph E Johnson Apparatus and method for handling logical and numerical uncertainty utilizing novel underlying precepts
WO2002019108A2 (en) 2000-08-28 2002-03-07 Verisity Ltd. Method for providing bitwise constraints for test generation

Also Published As

Publication number Publication date
WO2002019108A8 (en) 2004-04-29
US6918076B2 (en) 2005-07-12
US7613973B2 (en) 2009-11-03
DE60110811T2 (de) 2006-02-02
IL154585A0 (en) 2003-09-17
EP1314045A2 (de) 2003-05-28
WO2002019108A2 (en) 2002-03-07
WO2002019108A3 (en) 2002-07-25
US20050203720A1 (en) 2005-09-15
JP4652663B2 (ja) 2011-03-16
EP1314045B1 (de) 2005-05-11
AU2001282486A1 (en) 2002-03-13
DE60110811D1 (de) 2005-06-16
US20020049944A1 (en) 2002-04-25
JP2004507833A (ja) 2004-03-11

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Legal Events

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