ATE301848T1 - Mikrokontrollerarchitektur mit mikrocodierten peripheriegeräten - Google Patents

Mikrokontrollerarchitektur mit mikrocodierten peripheriegeräten

Info

Publication number
ATE301848T1
ATE301848T1 AT00122984T AT00122984T ATE301848T1 AT E301848 T1 ATE301848 T1 AT E301848T1 AT 00122984 T AT00122984 T AT 00122984T AT 00122984 T AT00122984 T AT 00122984T AT E301848 T1 ATE301848 T1 AT E301848T1
Authority
AT
Austria
Prior art keywords
microcode
peripheral devices
micro
microcontroller architecture
implemented
Prior art date
Application number
AT00122984T
Other languages
English (en)
Inventor
Sven Stefan Blixt
Original Assignee
Imsys Technologies Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imsys Technologies Ab filed Critical Imsys Technologies Ab
Application granted granted Critical
Publication of ATE301848T1 publication Critical patent/ATE301848T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/24—Loading of the microprogram
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4403—Processor initialisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Microcomputers (AREA)
  • Executing Machine-Instructions (AREA)
AT00122984T 1999-10-28 2000-10-23 Mikrokontrollerarchitektur mit mikrocodierten peripheriegeräten ATE301848T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/429,748 US7103759B1 (en) 1999-10-28 1999-10-28 Microcontroller architecture supporting microcode-implemented peripheral devices

Publications (1)

Publication Number Publication Date
ATE301848T1 true ATE301848T1 (de) 2005-08-15

Family

ID=23704580

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00122984T ATE301848T1 (de) 1999-10-28 2000-10-23 Mikrokontrollerarchitektur mit mikrocodierten peripheriegeräten

Country Status (4)

Country Link
US (1) US7103759B1 (de)
EP (1) EP1096370B1 (de)
AT (1) ATE301848T1 (de)
DE (1) DE60021827T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6976239B1 (en) * 2001-06-12 2005-12-13 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US7305567B1 (en) * 2002-03-01 2007-12-04 Cavium Networks, In. Decoupled architecture for data ciphering operations
US20080209076A1 (en) * 2007-02-22 2008-08-28 Wei Wang Method and system for fast ethernet controller operation using a virtual cpu
US8438549B1 (en) * 2009-09-15 2013-05-07 Sandia Corporation Data processing with microcode designed with source coding
US11797474B2 (en) * 2011-02-17 2023-10-24 Hyperion Core, Inc. High performance processor
CN103489432B (zh) * 2013-08-30 2016-04-13 小米科技有限责任公司 电子设备及资源显示方法
CN108595147B (zh) * 2018-01-02 2021-03-23 上海兆芯集成电路有限公司 具有级数运算执行电路的微处理器
DE102018115203B3 (de) 2018-06-25 2019-09-19 Hyundai Autron Co., Ltd. Multi-master-system, leistungssteuereinrichtung und verfahren zum betreiben des multi-master-systems
US10994718B2 (en) 2018-06-27 2021-05-04 Hyundai Autron Co., Ltd. Multi-master system, power controller and operating method of the multi-master system
CN113162585B (zh) * 2021-04-02 2023-02-17 浙江清华柔性电子技术研究院 脉冲控制方法、装置及电子设备
CN114579483B (zh) * 2022-03-02 2023-07-04 北京超智芯科技有限公司 一种基于软件实现外设的sdp芯片及方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3478322A (en) * 1967-05-23 1969-11-11 Ibm Data processor employing electronically changeable control storage
US3735363A (en) * 1971-04-07 1973-05-22 Burroughs Corp Information processing system employing stored microprogrammed processors and access free field memories
DE69230642T2 (de) * 1991-11-12 2001-05-23 Microchip Technology Inc., Chandler Automatischer programmierungs-mikrokontroller mit gespeichertem befehl zur programm-steuerung von externem speicher und verfahren
FR2700402B1 (fr) * 1993-01-13 1995-04-07 Sgs Thomson Microelectronics Microcontrôleur à mémoire électriquement programmable multimode.
US5781750A (en) 1994-01-11 1998-07-14 Exponential Technology, Inc. Dual-instruction-set architecture CPU with hidden software emulation mode
GB2307072B (en) 1994-06-10 1998-05-13 Advanced Risc Mach Ltd Interoperability with multiple instruction sets
US5481693A (en) 1994-07-20 1996-01-02 Exponential Technology, Inc. Shared register architecture for a dual-instruction-set CPU

Also Published As

Publication number Publication date
EP1096370A2 (de) 2001-05-02
DE60021827D1 (de) 2005-09-15
US7103759B1 (en) 2006-09-05
EP1096370A3 (de) 2004-05-06
DE60021827T2 (de) 2006-03-16
EP1096370B1 (de) 2005-08-10

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