ATE303649T1 - Verfahren zur synchronisation der auslesezeit eines hochgeschwindigkeitsspeichers - Google Patents

Verfahren zur synchronisation der auslesezeit eines hochgeschwindigkeitsspeichers

Info

Publication number
ATE303649T1
ATE303649T1 AT02718884T AT02718884T ATE303649T1 AT E303649 T1 ATE303649 T1 AT E303649T1 AT 02718884 T AT02718884 T AT 02718884T AT 02718884 T AT02718884 T AT 02718884T AT E303649 T1 ATE303649 T1 AT E303649T1
Authority
AT
Austria
Prior art keywords
read
flag signal
signal
memory
issuing
Prior art date
Application number
AT02718884T
Other languages
English (en)
Inventor
Jeffery W Janzen
Troy A Manning
Chris G Martin
Brent Keeth
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE303649T1 publication Critical patent/ATE303649T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
AT02718884T 2001-02-23 2002-02-01 Verfahren zur synchronisation der auslesezeit eines hochgeschwindigkeitsspeichers ATE303649T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/790,538 US6445624B1 (en) 2001-02-23 2001-02-23 Method of synchronizing read timing in a high speed memory system
PCT/US2002/002764 WO2002069341A2 (en) 2001-02-23 2002-02-01 A method of synchronizing read timing in a high speed memory system

Publications (1)

Publication Number Publication Date
ATE303649T1 true ATE303649T1 (de) 2005-09-15

Family

ID=25150999

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02718884T ATE303649T1 (de) 2001-02-23 2002-02-01 Verfahren zur synchronisation der auslesezeit eines hochgeschwindigkeitsspeichers

Country Status (8)

Country Link
US (3) US6445624B1 (de)
EP (1) EP1374244B1 (de)
JP (2) JP4030875B2 (de)
KR (1) KR100626506B1 (de)
CN (1) CN100385570C (de)
AT (1) ATE303649T1 (de)
DE (1) DE60205877T2 (de)
WO (1) WO2002069341A2 (de)

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Also Published As

Publication number Publication date
JP4030875B2 (ja) 2008-01-09
DE60205877T2 (de) 2006-06-29
WO2002069341A2 (en) 2002-09-06
DE60205877D1 (de) 2005-10-06
US6847583B2 (en) 2005-01-25
JP2007299522A (ja) 2007-11-15
US20020118578A1 (en) 2002-08-29
JP5415677B2 (ja) 2014-02-12
US6724666B2 (en) 2004-04-20
WO2002069341A3 (en) 2002-11-28
US20030002355A1 (en) 2003-01-02
EP1374244B1 (de) 2005-08-31
US6445624B1 (en) 2002-09-03
CN100385570C (zh) 2008-04-30
EP1374244A2 (de) 2004-01-02
CN1503974A (zh) 2004-06-09
KR20040005877A (ko) 2004-01-16
KR100626506B1 (ko) 2006-09-20
US20040160832A1 (en) 2004-08-19
JP2004525453A (ja) 2004-08-19

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