ATE304241T1 - Frequenzregelkreis, taktwiederherstellungsschaltung und empfänger - Google Patents

Frequenzregelkreis, taktwiederherstellungsschaltung und empfänger

Info

Publication number
ATE304241T1
ATE304241T1 AT02733040T AT02733040T ATE304241T1 AT E304241 T1 ATE304241 T1 AT E304241T1 AT 02733040 T AT02733040 T AT 02733040T AT 02733040 T AT02733040 T AT 02733040T AT E304241 T1 ATE304241 T1 AT E304241T1
Authority
AT
Austria
Prior art keywords
signal
generating
receiver
frequency control
clock recovery
Prior art date
Application number
AT02733040T
Other languages
English (en)
Inventor
Mihai A T Sanduleanu
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE304241T1 publication Critical patent/ATE304241T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Circuits Of Receivers In General (AREA)
  • Selective Calling Equipment (AREA)
AT02733040T 2001-05-31 2002-05-27 Frequenzregelkreis, taktwiederherstellungsschaltung und empfänger ATE304241T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP01202082 2001-05-31
PCT/IB2002/001871 WO2002097991A2 (en) 2001-05-31 2002-05-27 Frequency locked loop, clock recovery circuit and receiver

Publications (1)

Publication Number Publication Date
ATE304241T1 true ATE304241T1 (de) 2005-09-15

Family

ID=8180404

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02733040T ATE304241T1 (de) 2001-05-31 2002-05-27 Frequenzregelkreis, taktwiederherstellungsschaltung und empfänger

Country Status (7)

Country Link
US (1) US6943632B2 (de)
EP (1) EP1402642B1 (de)
JP (1) JP4283664B2 (de)
CN (1) CN1269312C (de)
AT (1) ATE304241T1 (de)
DE (1) DE60206049T2 (de)
WO (1) WO2002097991A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1942875B1 (de) * 2005-08-24 2015-08-12 Rubicon Research Private Limited Formulierung mit kontrollierter freisetzung
EP1958336A2 (de) * 2005-11-07 2008-08-20 Omnispread Communication, Inc. Nichtlineare regelschleifen als spreizspektrum-taktgenerator
CN101772151B (zh) * 2009-12-25 2013-05-08 中兴通讯股份有限公司 一种恢复时分复用输出的时钟信号的装置及方法
JP6185741B2 (ja) 2013-04-18 2017-08-23 ルネサスエレクトロニクス株式会社 周波数同期ループ回路及び半導体集積回路
US9455721B2 (en) 2014-10-09 2016-09-27 Texas Instruments Incorporated FLL oscillator/clock with an FLL control loop including a switched capacitor resistive divider

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61228707A (ja) * 1985-04-02 1986-10-11 Tokyo Keiki Co Ltd 周波数弁別回路
FR2646573B1 (fr) * 1989-04-28 1991-07-05 Alcatel Transmission Dispositif d'accord automatique de l'oscillateur commande en tension d'une boucle a verrouillage de phase
JP2768645B2 (ja) * 1995-01-19 1998-06-25 日本無線株式会社 低雑音発振回路用遅延検波回路
JPH1056488A (ja) * 1996-08-07 1998-02-24 Mitsubishi Electric Corp 周波数偏差検出器及びそれを用いた自動周波数制御回路
US6643346B1 (en) * 1999-02-23 2003-11-04 Rockwell Scientific Company Llc Frequency detection circuit for clock recovery

Also Published As

Publication number Publication date
CN1471760A (zh) 2004-01-28
US20040145422A1 (en) 2004-07-29
CN1269312C (zh) 2006-08-09
EP1402642A2 (de) 2004-03-31
WO2002097991A2 (en) 2002-12-05
JP2004520779A (ja) 2004-07-08
DE60206049T2 (de) 2006-06-14
JP4283664B2 (ja) 2009-06-24
WO2002097991A3 (en) 2003-09-18
DE60206049D1 (de) 2005-10-13
US6943632B2 (en) 2005-09-13
EP1402642B1 (de) 2005-09-07

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties