ATE309616T1 - Verkapselung des anschlusslots zur aufrechterhaltung der genauigkeit der anschlussposition - Google Patents

Verkapselung des anschlusslots zur aufrechterhaltung der genauigkeit der anschlussposition

Info

Publication number
ATE309616T1
ATE309616T1 AT02799643T AT02799643T ATE309616T1 AT E309616 T1 ATE309616 T1 AT E309616T1 AT 02799643 T AT02799643 T AT 02799643T AT 02799643 T AT02799643 T AT 02799643T AT E309616 T1 ATE309616 T1 AT E309616T1
Authority
AT
Austria
Prior art keywords
connector
encapsulating
accuracy
maintain
slot
Prior art date
Application number
AT02799643T
Other languages
English (en)
Inventor
Michele J Berry
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE309616T1 publication Critical patent/ATE309616T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1031—Surface mounted metallic connector elements
    • H05K2201/10318—Surface mounted metallic pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Multi-Conductor Connections (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Flanged Joints, Insulating Joints, And Other Joints (AREA)
  • Mechanical Coupling Of Light Guides (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
AT02799643T 2001-09-27 2002-09-26 Verkapselung des anschlusslots zur aufrechterhaltung der genauigkeit der anschlussposition ATE309616T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/965,555 US6974765B2 (en) 2001-09-27 2001-09-27 Encapsulation of pin solder for maintaining accuracy in pin position
PCT/US2002/030625 WO2003028100A2 (en) 2001-09-27 2002-09-26 Encapsulation of pin solder for maintaining accuracy in pin position

Publications (1)

Publication Number Publication Date
ATE309616T1 true ATE309616T1 (de) 2005-11-15

Family

ID=25510133

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02799643T ATE309616T1 (de) 2001-09-27 2002-09-26 Verkapselung des anschlusslots zur aufrechterhaltung der genauigkeit der anschlussposition

Country Status (6)

Country Link
US (2) US6974765B2 (de)
EP (1) EP1430532B1 (de)
CN (1) CN100350603C (de)
AT (1) ATE309616T1 (de)
DE (1) DE60207282T2 (de)
WO (1) WO2003028100A2 (de)

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US8178435B2 (en) 1998-12-21 2012-05-15 Megica Corporation High performance system-on-chip inductor using post passivation process
US8421158B2 (en) 1998-12-21 2013-04-16 Megica Corporation Chip structure with a passive device and method for forming the same
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US6974765B2 (en) * 2001-09-27 2005-12-13 Intel Corporation Encapsulation of pin solder for maintaining accuracy in pin position
US6911726B2 (en) * 2002-06-07 2005-06-28 Intel Corporation Microelectronic packaging and methods for thermally protecting package interconnects and components
TWI236763B (en) * 2003-05-27 2005-07-21 Megic Corp High performance system-on-chip inductor using post passivation process
US7417305B2 (en) * 2004-08-26 2008-08-26 Micron Technology, Inc. Electronic devices at the wafer level having front side and edge protection material and systems including the devices
US8384189B2 (en) * 2005-03-29 2013-02-26 Megica Corporation High performance system-on-chip using post passivation process
US20080283999A1 (en) * 2007-05-18 2008-11-20 Eric Tosaya Chip Package with Pin Stabilization Layer
JP4993754B2 (ja) * 2008-02-22 2012-08-08 新光電気工業株式会社 Ｐｇａ型配線基板及びその製造方法
JP4961398B2 (ja) * 2008-06-30 2012-06-27 株式会社日立製作所 半導体装置
JP5281346B2 (ja) * 2008-09-18 2013-09-04 新光電気工業株式会社 半導体装置及びその製造方法
CN102291974B (zh) * 2010-06-18 2014-04-02 亚旭电脑股份有限公司 切边定位型焊接垫及防止引脚偏移的方法
JP2012164965A (ja) * 2011-01-21 2012-08-30 Ngk Spark Plug Co Ltd 配線基板及びその製造方法
EP3859776B1 (de) * 2020-01-31 2026-02-25 Infineon Technologies AG Leistungshalbleiterbauelement und verfahren zur herstellung eines leistungshalbleiterbauelements
EP4503871A1 (de) * 2023-08-01 2025-02-05 Infineon Technologies AG Verfahren zum verbinden zweier verbindungspartner

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US5088914A (en) * 1990-05-11 1992-02-18 Romano Brambilla Double flighted extrusion screw
US5196251A (en) 1991-04-30 1993-03-23 International Business Machines Corporation Ceramic substrate having a protective coating thereon and a method for protecting a ceramic substrate
DE69220333D1 (de) * 1991-12-11 1997-07-17 Ibm Elektronische Baugruppe mit schützendem Verkapselungsmaterial
US5469333A (en) * 1993-05-05 1995-11-21 International Business Machines Corporation Electronic package assembly with protective encapsulant material on opposing sides not having conductive leads
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US6974765B2 (en) * 2001-09-27 2005-12-13 Intel Corporation Encapsulation of pin solder for maintaining accuracy in pin position
US6610559B2 (en) * 2001-11-16 2003-08-26 Indium Corporation Of America Integrated void-free process for assembling a solder bumped chip
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Also Published As

Publication number Publication date
US7211888B2 (en) 2007-05-01
US6974765B2 (en) 2005-12-13
US20030057572A1 (en) 2003-03-27
EP1430532A2 (de) 2004-06-23
WO2003028100A3 (en) 2003-11-20
US20050275094A1 (en) 2005-12-15
DE60207282D1 (de) 2005-12-15
DE60207282T2 (de) 2006-05-24
CN100350603C (zh) 2007-11-21
EP1430532B1 (de) 2005-11-09
CN1572023A (zh) 2005-01-26
WO2003028100A2 (en) 2003-04-03

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