ATE312411T1 - Doppeldamaszen-zwischenverbindungen ohne ätzstoppschicht mittels alternierender ilds - Google Patents

Doppeldamaszen-zwischenverbindungen ohne ätzstoppschicht mittels alternierender ilds

Info

Publication number
ATE312411T1
ATE312411T1 AT02768930T AT02768930T ATE312411T1 AT E312411 T1 ATE312411 T1 AT E312411T1 AT 02768930 T AT02768930 T AT 02768930T AT 02768930 T AT02768930 T AT 02768930T AT E312411 T1 ATE312411 T1 AT E312411T1
Authority
AT
Austria
Prior art keywords
ilds
alternate
stop layer
damascen
double
Prior art date
Application number
AT02768930T
Other languages
English (en)
Inventor
Lawrence Wong
Patrick Morrow
Jihperng Leu
Andrew Ott
Grant Kloster
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE312411T1 publication Critical patent/ATE312411T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Pressure Sensors (AREA)
  • Optical Communication System (AREA)
  • Slot Machines And Peripheral Devices (AREA)
  • Drying Of Semiconductors (AREA)
AT02768930T 2001-09-28 2002-09-27 Doppeldamaszen-zwischenverbindungen ohne ätzstoppschicht mittels alternierender ilds ATE312411T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/968,459 US6992391B2 (en) 2001-09-28 2001-09-28 Dual-damascene interconnects without an etch stop layer by alternating ILDs
PCT/US2002/031159 WO2003028092A2 (en) 2001-09-28 2002-09-27 Dual-damascene interconnects without an etch stop layer by alternating ilds

Publications (1)

Publication Number Publication Date
ATE312411T1 true ATE312411T1 (de) 2005-12-15

Family

ID=25514297

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02768930T ATE312411T1 (de) 2001-09-28 2002-09-27 Doppeldamaszen-zwischenverbindungen ohne ätzstoppschicht mittels alternierender ilds

Country Status (8)

Country Link
US (2) US6992391B2 (de)
EP (1) EP1430525B1 (de)
CN (1) CN1263114C (de)
AT (1) ATE312411T1 (de)
DE (1) DE60207879T2 (de)
MY (1) MY130377A (de)
TW (1) TW559958B (de)
WO (1) WO2003028092A2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI278962B (en) * 2002-04-12 2007-04-11 Hitachi Ltd Semiconductor device
US6902954B2 (en) * 2003-03-31 2005-06-07 Intel Corporation Temperature sustaining flip chip assembly process
US7157380B2 (en) * 2003-12-24 2007-01-02 Intel Corporation Damascene process for fabricating interconnect layers in an integrated circuit
US20060157776A1 (en) * 2005-01-20 2006-07-20 Cheng-Hung Chang System and method for contact module processing
US7867779B2 (en) 2005-02-03 2011-01-11 Air Products And Chemicals, Inc. System and method comprising same for measurement and/or analysis of particles in gas stream
CN101667555B (zh) * 2005-12-07 2012-06-27 佳能株式会社 使用双镶嵌工艺制造半导体器件的方法以及制造具有连通孔的制品的方法
US7790631B2 (en) * 2006-11-21 2010-09-07 Intel Corporation Selective deposition of a dielectric on a self-assembled monolayer-adsorbed metal
TWI320588B (en) * 2006-12-27 2010-02-11 Siliconware Precision Industries Co Ltd Semiconductor device having conductive bumps and fabrication methodthereof
US8120114B2 (en) * 2006-12-27 2012-02-21 Intel Corporation Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate
US8154121B2 (en) * 2008-02-26 2012-04-10 Intel Corporation Polymer interlayer dielectric and passivation materials for a microelectronic device
US20150162277A1 (en) 2013-12-05 2015-06-11 International Business Machines Corporation Advanced interconnect with air gap
US9214429B2 (en) 2013-12-05 2015-12-15 Stmicroelectronics, Inc. Trench interconnect having reduced fringe capacitance
US12334398B2 (en) 2021-08-23 2025-06-17 International Business Machines Corporation Multilayer dielectric stack for damascene top-via integration

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6197696B1 (en) 1998-03-26 2001-03-06 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
US6127258A (en) * 1998-06-25 2000-10-03 Motorola Inc. Method for forming a semiconductor device
TW437040B (en) 1998-08-12 2001-05-28 Applied Materials Inc Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics
US6165898A (en) * 1998-10-23 2000-12-26 Taiwan Semiconductor Manufacturing Company Dual damascene patterned conductor layer formation method without etch stop layer
US6287961B1 (en) * 1999-01-04 2001-09-11 Taiwan Semiconductor Manufacturing Company Dual damascene patterned conductor layer formation method without etch stop layer
US6770975B2 (en) * 1999-06-09 2004-08-03 Alliedsignal Inc. Integrated circuits with multiple low dielectric-constant inter-metal dielectrics
US6576550B1 (en) * 2000-06-30 2003-06-10 Infineon, Ag ‘Via first’ dual damascene process for copper metallization
US6395632B1 (en) * 2000-08-31 2002-05-28 Micron Technology, Inc. Etch stop in damascene interconnect structure and method of making
US6861347B2 (en) * 2001-05-17 2005-03-01 Samsung Electronics Co., Ltd. Method for forming metal wiring layer of semiconductor device
US6943451B2 (en) * 2001-07-02 2005-09-13 International Business Machines Corporation Semiconductor devices containing a discontinuous cap layer and methods for forming same
KR100428791B1 (ko) * 2002-04-17 2004-04-28 삼성전자주식회사 저유전율 절연막을 이용한 듀얼 다마신 배선 형성방법
US20040056366A1 (en) * 2002-09-25 2004-03-25 Maiz Jose A. A method of forming surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvement
US7094683B2 (en) * 2003-08-04 2006-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Dual damascene method for ultra low K dielectrics

Also Published As

Publication number Publication date
US20030064580A1 (en) 2003-04-03
EP1430525B1 (de) 2005-12-07
DE60207879T2 (de) 2006-08-17
CN1535477A (zh) 2004-10-06
DE60207879D1 (de) 2006-01-12
MY130377A (en) 2007-06-29
US20050208753A1 (en) 2005-09-22
WO2003028092A3 (en) 2003-08-28
TW559958B (en) 2003-11-01
EP1430525A2 (de) 2004-06-23
WO2003028092A2 (en) 2003-04-03
CN1263114C (zh) 2006-07-05
US6992391B2 (en) 2006-01-31

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Legal Events

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