ATE314659T1 - Topologierekonfiguration einer prüfschaltung und verwendungsverfahren - Google Patents

Topologierekonfiguration einer prüfschaltung und verwendungsverfahren

Info

Publication number
ATE314659T1
ATE314659T1 AT02779830T AT02779830T ATE314659T1 AT E314659 T1 ATE314659 T1 AT E314659T1 AT 02779830 T AT02779830 T AT 02779830T AT 02779830 T AT02779830 T AT 02779830T AT E314659 T1 ATE314659 T1 AT E314659T1
Authority
AT
Austria
Prior art keywords
test
protocol
test circuit
topology
topology configuration
Prior art date
Application number
AT02779830T
Other languages
English (en)
Inventor
Lonnie C Goff
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE314659T1 publication Critical patent/ATE314659T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
AT02779830T 2001-11-30 2002-11-05 Topologierekonfiguration einer prüfschaltung und verwendungsverfahren ATE314659T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/997,784 US6934898B1 (en) 2001-11-30 2001-11-30 Test circuit topology reconfiguration and utilization techniques
PCT/IB2002/004661 WO2003046724A2 (en) 2001-11-30 2002-11-05 Test circuit topology reconfiguration and utilization method

Publications (1)

Publication Number Publication Date
ATE314659T1 true ATE314659T1 (de) 2006-01-15

Family

ID=25544393

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02779830T ATE314659T1 (de) 2001-11-30 2002-11-05 Topologierekonfiguration einer prüfschaltung und verwendungsverfahren

Country Status (6)

Country Link
US (2) US6934898B1 (de)
EP (1) EP1459080B1 (de)
AT (1) ATE314659T1 (de)
AU (1) AU2002343162A1 (de)
DE (1) DE60208442T2 (de)
WO (1) WO2003046724A2 (de)

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Also Published As

Publication number Publication date
AU2002343162A8 (en) 2003-06-10
EP1459080B1 (de) 2005-12-28
US20050257087A1 (en) 2005-11-17
WO2003046724A3 (en) 2004-06-10
DE60208442T2 (de) 2006-08-31
AU2002343162A1 (en) 2003-06-10
WO2003046724A2 (en) 2003-06-05
US6934898B1 (en) 2005-08-23
DE60208442D1 (de) 2006-02-02
EP1459080A2 (de) 2004-09-22

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