ATE321362T1 - Halbleiteranordnung mit weichen elektrischen anschlüssen, bauteil damit und seine herstellungsverfahren - Google Patents

Halbleiteranordnung mit weichen elektrischen anschlüssen, bauteil damit und seine herstellungsverfahren

Info

Publication number
ATE321362T1
ATE321362T1 AT02761321T AT02761321T ATE321362T1 AT E321362 T1 ATE321362 T1 AT E321362T1 AT 02761321 T AT02761321 T AT 02761321T AT 02761321 T AT02761321 T AT 02761321T AT E321362 T1 ATE321362 T1 AT E321362T1
Authority
AT
Austria
Prior art keywords
compliant
dielectric layer
bumps
electrically conductive
semiconductor device
Prior art date
Application number
AT02761321T
Other languages
English (en)
Inventor
Michael A Lutz
Original Assignee
Dow Corning
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dow Corning filed Critical Dow Corning
Application granted granted Critical
Publication of ATE321362T1 publication Critical patent/ATE321362T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
AT02761321T 2001-09-12 2002-08-12 Halbleiteranordnung mit weichen elektrischen anschlüssen, bauteil damit und seine herstellungsverfahren ATE321362T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/952,337 US20030047339A1 (en) 2001-09-12 2001-09-12 Semiconductor device with compliant electrical terminals, apparatus including the semiconductor device, and methods for forming same

Publications (1)

Publication Number Publication Date
ATE321362T1 true ATE321362T1 (de) 2006-04-15

Family

ID=25492801

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02761321T ATE321362T1 (de) 2001-09-12 2002-08-12 Halbleiteranordnung mit weichen elektrischen anschlüssen, bauteil damit und seine herstellungsverfahren

Country Status (10)

Country Link
US (1) US20030047339A1 (de)
EP (1) EP1428256B1 (de)
JP (1) JP4771658B2 (de)
KR (1) KR100888712B1 (de)
AT (1) ATE321362T1 (de)
AU (1) AU2002326597A1 (de)
CA (1) CA2459386A1 (de)
DE (1) DE60210109T2 (de)
TW (1) TW569413B (de)
WO (1) WO2003023855A2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150307997A1 (en) * 2002-10-29 2015-10-29 Microfabrica Inc. Methods for Fabricating Metal Structures Incorporating Dielectric Sheets
US7294929B2 (en) * 2003-12-30 2007-11-13 Texas Instruments Incorporated Solder ball pad structure
CN100490136C (zh) * 2005-01-12 2009-05-20 台湾薄膜电晶体液晶显示器产业协会 倒装芯片的装置
US20090256256A1 (en) * 2008-04-11 2009-10-15 Infineon Technologies Ag Electronic Device and Method of Manufacturing Same
TWI462676B (zh) * 2009-02-13 2014-11-21 千住金屬工業股份有限公司 The solder bumps for the circuit substrate are formed using the transfer sheet
US9293402B2 (en) 2012-04-13 2016-03-22 Lapis Semiconductor Co., Ltd. Device with pillar-shaped components
JP5128712B1 (ja) * 2012-04-13 2013-01-23 ラピスセミコンダクタ株式会社 半導体装置
JP2016184620A (ja) * 2015-03-25 2016-10-20 大日本印刷株式会社 多層配線構造体
JP2016184619A (ja) * 2015-03-25 2016-10-20 大日本印刷株式会社 多層配線構造体
JP2015167254A (ja) * 2015-05-21 2015-09-24 株式会社テラプローブ 半導体装置、その実装構造及びその製造方法
KR101897653B1 (ko) * 2017-03-06 2018-09-12 엘비세미콘 주식회사 컴플라이언트 범프의 제조방법
US10748850B2 (en) 2018-03-15 2020-08-18 Semiconductor Components Industries, Llc Thinned semiconductor package and related methods
US11749616B2 (en) * 2017-10-05 2023-09-05 Texas Instruments Incorporated Industrial chip scale package for microelectronic device
US10923365B2 (en) * 2018-10-28 2021-02-16 Richwave Technology Corp. Connection structure and method for forming the same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5074947A (en) * 1989-12-18 1991-12-24 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
US6114187A (en) * 1997-01-11 2000-09-05 Microfab Technologies, Inc. Method for preparing a chip scale package and product produced by the method
US5937320A (en) * 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
JP2000208664A (ja) * 1999-01-13 2000-07-28 Matsushita Electric Ind Co Ltd 半導体パッケ―ジおよびその製造方法、並びに、半導体チップ実装体およびその製造方法
JP2000228417A (ja) * 1999-02-04 2000-08-15 Sony Corp 半導体装置、電子モジュール及び電子機器、並びに半導体装置の製造方法
US6271107B1 (en) * 1999-03-31 2001-08-07 Fujitsu Limited Semiconductor with polymeric layer
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
JP4526651B2 (ja) * 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 半導体装置
JP3339478B2 (ja) * 1999-10-07 2002-10-28 日本電気株式会社 フリップチップ型半導体装置とその製造方法
JP2001144204A (ja) * 1999-11-16 2001-05-25 Nec Corp 半導体装置及びその製造方法
JP2002118199A (ja) * 2000-10-10 2002-04-19 Mitsubishi Electric Corp 半導体装置

Also Published As

Publication number Publication date
US20030047339A1 (en) 2003-03-13
KR20040047822A (ko) 2004-06-05
JP2005503020A (ja) 2005-01-27
EP1428256A2 (de) 2004-06-16
AU2002326597A1 (en) 2003-03-24
DE60210109D1 (de) 2006-05-11
WO2003023855A3 (en) 2003-12-11
TW569413B (en) 2004-01-01
DE60210109T2 (de) 2006-11-09
CA2459386A1 (en) 2003-03-20
EP1428256B1 (de) 2006-03-22
WO2003023855A2 (en) 2003-03-20
JP4771658B2 (ja) 2011-09-14
KR100888712B1 (ko) 2009-03-17

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Legal Events

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