ATE327587T1 - Verfahren und vorrichtung zur diagnose von ausfällen in einer integrierten schaltung unter verwendung von techniken des typs design-for- debug (dfd) - Google Patents

Verfahren und vorrichtung zur diagnose von ausfällen in einer integrierten schaltung unter verwendung von techniken des typs design-for- debug (dfd)

Info

Publication number
ATE327587T1
ATE327587T1 AT02709362T AT02709362T ATE327587T1 AT E327587 T1 ATE327587 T1 AT E327587T1 AT 02709362 T AT02709362 T AT 02709362T AT 02709362 T AT02709362 T AT 02709362T AT E327587 T1 ATE327587 T1 AT E327587T1
Authority
AT
Austria
Prior art keywords
dfd
dbg
run
cores
scan
Prior art date
Application number
AT02709362T
Other languages
English (en)
Inventor
Laung-Terny Wang
Ming-Tung Chang
Shyh-Horng Lin
Hao-Jan Chao
Jachee Lee
Hsin-Po Wang
Xiaoqing Wen
Po-Ching Hsu
Shih-Chia Kao
Meng-Chyi Lin
Sen-Wei Tsai
Chi-Chan Hsu
Original Assignee
Syntest Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Syntest Technologies Inc filed Critical Syntest Technologies Inc
Application granted granted Critical
Publication of ATE327587T1 publication Critical patent/ATE327587T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
AT02709362T 2001-03-01 2002-02-28 Verfahren und vorrichtung zur diagnose von ausfällen in einer integrierten schaltung unter verwendung von techniken des typs design-for- debug (dfd) ATE327587T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US27206401P 2001-03-01 2001-03-01
US10/086,214 US7191373B2 (en) 2001-03-01 2002-02-27 Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

Publications (1)

Publication Number Publication Date
ATE327587T1 true ATE327587T1 (de) 2006-06-15

Family

ID=26774484

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02709362T ATE327587T1 (de) 2001-03-01 2002-02-28 Verfahren und vorrichtung zur diagnose von ausfällen in einer integrierten schaltung unter verwendung von techniken des typs design-for- debug (dfd)

Country Status (5)

Country Link
US (2) US7191373B2 (de)
EP (1) EP1364436B1 (de)
AT (1) ATE327587T1 (de)
DE (1) DE60211659T2 (de)
WO (1) WO2002071567A1 (de)

Families Citing this family (131)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6823497B2 (en) * 1999-11-30 2004-11-23 Synplicity, Inc. Method and user interface for debugging an electronic system
US7356786B2 (en) * 1999-11-30 2008-04-08 Synplicity, Inc. Method and user interface for debugging an electronic system
US7240303B1 (en) 1999-11-30 2007-07-03 Synplicity, Inc. Hardware/software co-debugging in a hardware description language
US7222315B2 (en) 2000-11-28 2007-05-22 Synplicity, Inc. Hardware-based HDL code coverage and design analysis
DE60206845T2 (de) * 2001-06-20 2006-07-06 Broadcom Corp., Irvine Testsystem
JP2003121499A (ja) * 2001-10-09 2003-04-23 Hitachi Ltd 組込みテスト機能付き半導体集積回路、テストコード生成プログラムから成る電子設計データを保存する記憶媒体、該半導体集積回路のテスト方法、テストコード生成自動化方法及びそのプログラム
US6996760B2 (en) * 2001-10-12 2006-02-07 Sun Microsystems ASIC BIST employing stored indications of completion
US7055135B2 (en) * 2002-05-06 2006-05-30 Sun Microsystems, Inc. Method for debugging an integrated circuit
US7827510B1 (en) 2002-06-07 2010-11-02 Synopsys, Inc. Enhanced hardware debugging with embedded FPGAS in a hardware description language
US7111199B2 (en) * 2002-07-08 2006-09-19 Lsi Logic Corporation Built-in debug feature for complex VLSI chip
US7213216B2 (en) * 2002-08-09 2007-05-01 Synplicity, Inc. Method and system for debugging using replicated logic and trigger logic
US6904576B2 (en) * 2002-08-09 2005-06-07 Synplicity, Inc. Method and system for debugging using replicated logic
WO2004038436A1 (ja) * 2002-10-24 2004-05-06 Advantest Corporation 目標値の探索回路、目標値の探索方法及びこれを用いた半導体試験装置
US20040153926A1 (en) * 2002-10-30 2004-08-05 Abdel-Hafez Khader S. Method and apparatus for testing asynchronous set/reset faults in a scan-based integrated circuit
US7302624B2 (en) * 2003-02-13 2007-11-27 Janusz Rajski Adaptive fault diagnosis of compressed test responses
US7509550B2 (en) 2003-02-13 2009-03-24 Janusz Rajski Fault diagnosis of compressed test responses
US7437640B2 (en) 2003-02-13 2008-10-14 Janusz Rajski Fault diagnosis of compressed test responses having one or more unknown states
US7502976B2 (en) * 2003-02-13 2009-03-10 Ross Don E Testing embedded memories in an integrated circuit
US7085976B1 (en) * 2003-02-18 2006-08-01 Xilinx, Inc. Method and apparatus for hardware co-simulation clocking
US7155649B2 (en) * 2003-03-12 2006-12-26 Matsushita Electric Industrial Co., Ltd. Scan test control method and scan test circuit
US7975197B2 (en) * 2003-03-31 2011-07-05 Lsi Corporation On-chip scan clock generator for ASIC testing
US7080789B2 (en) * 2003-05-09 2006-07-25 Stmicroelectronics, Inc. Smart card including a JTAG test controller and related methods
US7216274B2 (en) * 2003-06-26 2007-05-08 Intel Corporation Flexible scan architecture
CN100370264C (zh) * 2003-07-28 2008-02-20 华为技术有限公司 一种自动识别电路板类型的方法
EP1505400A1 (de) * 2003-08-07 2005-02-09 Texas Instruments Incorporated Modulator für die Scan-Erfassungs-Frequenz
US7219265B2 (en) * 2003-12-29 2007-05-15 Agere Systems Inc. System and method for debugging system-on-chips
US7055117B2 (en) * 2003-12-29 2006-05-30 Agere Systems, Inc. System and method for debugging system-on-chips using single or n-cycle stepping
JP2007518988A (ja) * 2004-01-19 2007-07-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 複数のクロックドメインを備える回路のテスティング
US20050240834A1 (en) * 2004-03-30 2005-10-27 Aviation Communication & Surveillance Systems Llc Systems and methods for controlling extended functions
EP1584938B1 (de) * 2004-04-07 2008-05-21 STMicroelectronics Limited Hochgeschwindigkeitsprüfung von integrierten Schaltungen
US7707472B1 (en) * 2004-05-17 2010-04-27 Altera Corporation Method and apparatus for routing efficient built-in self test for on-chip circuit blocks
US7814377B2 (en) * 2004-07-09 2010-10-12 Sandisk Corporation Non-volatile memory system with self test capability
US7627798B2 (en) * 2004-10-08 2009-12-01 Kabushiki Kaisha Toshiba Systems and methods for circuit testing using LBIST
JP2006350707A (ja) * 2005-06-16 2006-12-28 Hitachi Ltd 検出手段の故障診断装置
US7665002B1 (en) * 2005-12-14 2010-02-16 Advanced Micro Devices, Inc. Multi-core integrated circuit with shared debug port
JP2007163845A (ja) * 2005-12-14 2007-06-28 Oki Electric Ind Co Ltd 音源システム
US7949920B2 (en) * 2006-04-19 2011-05-24 Texas Instruments Incorporated DFT techniques to reduce test time and power for SoCs
US7539913B2 (en) * 2006-07-05 2009-05-26 Via Technologies, Inc. Systems and methods for chip testing
US20080016421A1 (en) * 2006-07-13 2008-01-17 International Business Machines Corporation Method and apparatus for providing programmable control of built-in self test
WO2008008546A2 (en) * 2006-07-14 2008-01-17 Xinghao Chen Universal reconfigurable scan architecture
JPWO2008059638A1 (ja) * 2006-11-13 2010-02-25 パナソニック株式会社 半導体装置
US8327454B2 (en) * 2006-11-14 2012-12-04 Sandisk Technologies Inc. Method for allowing multiple users to access preview content
US20080114693A1 (en) * 2006-11-14 2008-05-15 Fabrice Jogand-Coulomb Method for allowing content protected by a first DRM system to be accessed by a second DRM system
US8763110B2 (en) 2006-11-14 2014-06-24 Sandisk Technologies Inc. Apparatuses for binding content to a separate memory device
US8079071B2 (en) * 2006-11-14 2011-12-13 SanDisk Technologies, Inc. Methods for accessing content based on a session ticket
US20080114772A1 (en) * 2006-11-14 2008-05-15 Fabrice Jogand-Coulomb Method for connecting to a network location associated with content
DE102006053483B4 (de) 2006-11-14 2019-09-12 Robert Bosch Gmbh Verfahren zur Überwachung einer Klopfregelung und Vorrichtung zur Klopfregelung einer Brennkraftmaschine
US20080133989A1 (en) * 2006-12-05 2008-06-05 Sony Computer Entertainment Inc. Method And Apparatus For Scan Chain Circuit AC Test
US8112683B1 (en) * 2007-02-06 2012-02-07 Marvell International Ltd. System and application debugging
KR101047533B1 (ko) * 2007-02-23 2011-07-08 삼성전자주식회사 멀티 페이즈 스캔체인을 구동하는 시스템온칩과 그 방법
US7984448B2 (en) * 2007-06-26 2011-07-19 International Business Machines Corporation Mechanism to support generic collective communication across a variety of programming models
US8230433B2 (en) 2007-06-26 2012-07-24 International Business Machines Corporation Shared performance monitor in a multiprocessor system
US7793038B2 (en) 2007-06-26 2010-09-07 International Business Machines Corporation System and method for programmable bank selection for banked memory subsystems
US8458282B2 (en) 2007-06-26 2013-06-04 International Business Machines Corporation Extended write combining using a write continuation hint flag
US8468416B2 (en) 2007-06-26 2013-06-18 International Business Machines Corporation Combined group ECC protection and subgroup parity protection
US8140925B2 (en) * 2007-06-26 2012-03-20 International Business Machines Corporation Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan
US7877551B2 (en) * 2007-06-26 2011-01-25 International Business Machines Corporation Programmable partitioning for high-performance coherence domains in a multiprocessor system
US8756350B2 (en) 2007-06-26 2014-06-17 International Business Machines Corporation Method and apparatus for efficiently tracking queue entries relative to a timestamp
US8509255B2 (en) 2007-06-26 2013-08-13 International Business Machines Corporation Hardware packet pacing using a DMA in a parallel computer
US7802025B2 (en) 2007-06-26 2010-09-21 International Business Machines Corporation DMA engine for repeating communication patterns
US7827391B2 (en) 2007-06-26 2010-11-02 International Business Machines Corporation Method and apparatus for single-stepping coherence events in a multiprocessor system under software control
US8010875B2 (en) 2007-06-26 2011-08-30 International Business Machines Corporation Error correcting code with chip kill capability and power saving enhancement
US8103832B2 (en) * 2007-06-26 2012-01-24 International Business Machines Corporation Method and apparatus of prefetching streams of varying prefetch depth
US7886084B2 (en) 2007-06-26 2011-02-08 International Business Machines Corporation Optimized collectives using a DMA on a parallel computer
US8108738B2 (en) 2007-06-26 2012-01-31 International Business Machines Corporation Data eye monitor method and apparatus
US8032892B2 (en) * 2007-06-26 2011-10-04 International Business Machines Corporation Message passing with a limited number of DMA byte counters
US20090089636A1 (en) * 2007-10-01 2009-04-02 Fernsler Matthew E Method and Apparatus for Logic Built In Self Test (LBIST) Fault Detection in Multi-Core Processors
US7870448B2 (en) * 2007-12-18 2011-01-11 International Business Machines Corporation In system diagnostics through scan matrix
US7805644B2 (en) * 2007-12-29 2010-09-28 Texas Instruments Incorporated Multiple pBIST controllers
JP2009216619A (ja) * 2008-03-12 2009-09-24 Texas Instr Japan Ltd 半導体集積回路装置
US8046651B2 (en) 2008-04-02 2011-10-25 Texas Instruments Incorporated Compare circuit receiving scan register and inverted clock flip-flop data
US7895490B2 (en) * 2008-05-20 2011-02-22 International Business Machines Corporation Method and system for testing an electronic circuit to identify multiple defects
US7934134B2 (en) * 2008-06-05 2011-04-26 International Business Machines Corporation Method and apparatus for performing logic built-in self-testing of an integrated circuit
US8829940B2 (en) * 2008-09-26 2014-09-09 Nxp, B.V. Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device
US8136059B2 (en) * 2008-10-24 2012-03-13 International Business Machines Corporation Indeterminate state logic insertion
US7921346B2 (en) * 2008-10-31 2011-04-05 International Business Machines Corporation Verification of array built-in self-test (ABIST) design-for-test/design-for-diagnostics (DFT/DFD)
US8418008B2 (en) * 2008-12-18 2013-04-09 Lsi Corporation Test technique to apply a variable scan clock including a scan clock modifier on an integrated circuit
CA3000710C (en) * 2009-01-15 2022-04-12 Electronic Warfare Associates, Inc. Systems and methods of implementing remote boundary scan features
US8106801B2 (en) * 2009-02-12 2012-01-31 Qualcomm, Incorporated Methods and apparatus for built in self test of analog-to-digital convertors
JP5279901B2 (ja) * 2009-05-27 2013-09-04 三菱電機株式会社 シーケンスプログラムのデバッグ装置、デバッグ方法、及び、プログラム
US8381052B2 (en) * 2009-11-10 2013-02-19 International Business Machines Corporation Circuit and method for efficient memory repair
EP2365441B1 (de) * 2010-03-08 2018-01-24 Mobileye Vision Technologies Ltd. Haltepunkt-Methodologie für Einchipsysteme
TWI482166B (zh) * 2010-03-19 2015-04-21 Hoy Technology Co Ltd Hybrid self - test circuit structure
US8281199B2 (en) * 2010-05-03 2012-10-02 Hoy Technologies, Co., Ltd. Hybrid self-test circuit structure
JP2012145467A (ja) * 2011-01-13 2012-08-02 Renesas Electronics Corp 半導体集積回路及び電源電圧適応制御システム
TWI557746B (zh) 2011-05-10 2016-11-11 電子戰協會公司 實施微電腦為基的電路之內容驗證的系統及方法
US8671320B2 (en) * 2011-06-21 2014-03-11 Lsi Corporation Integrated circuit comprising scan test circuitry with controllable number of capture pulses
TWI546692B (zh) 2011-10-27 2016-08-21 電子戰協會公司 包括與已知電路板資訊有關之電路測試及驗證等特徵的裝置鑑別之系統及方法
US20130173978A1 (en) * 2012-01-01 2013-07-04 Hiroyuki Sasaya Multiple input and/or output data for boundary scan nodes
US8583973B1 (en) * 2013-02-22 2013-11-12 Lsi Corporation Stored-pattern logic self-testing with serial communication
US20140258780A1 (en) * 2013-03-05 2014-09-11 Micron Technology, Inc. Memory controllers including test mode engines and methods for repair of memory over busses used during normal operation of the memory
US20140281717A1 (en) * 2013-03-14 2014-09-18 Nisar Ahmed Built-in self test (bist) with clock control
KR102066661B1 (ko) 2013-09-02 2020-01-15 삼성전자 주식회사 스캔-체인으로 연결된 플립-플롭들의 값들을 jtag 인터페이스를 이용하여 재구성할 수 있는 집적 회로, 이의 동작 방법, 및 상기 집적 회로를 포함하는 장치들
US9110135B2 (en) * 2013-09-23 2015-08-18 International Business Machines Corporation Chip testing with exclusive OR
US9632141B2 (en) * 2014-06-26 2017-04-25 Oracle International Corporation Simultaneous transition testing of different clock domains in a digital integrated circuit
CN105988075B (zh) 2015-02-17 2019-12-20 恩智浦美国有限公司 用于扫描测试的增强状态监视器
WO2016146168A1 (en) * 2015-03-17 2016-09-22 Huawei Technologies Co., Ltd. Mixed-signal integrated circuit
CN105486999A (zh) * 2015-11-27 2016-04-13 中国电子科技集团公司第三十八研究所 基于pxi总线的边界扫描数字电路测试系统及其测试方法
TWI625534B (zh) * 2015-12-21 2018-06-01 瑞昱半導體股份有限公司 透過掃描測試的掃描鏈所執行的除錯方法及相關電路系統
US10234503B2 (en) * 2015-12-21 2019-03-19 Realtek Semiconductor Corp. Debugging method executed via scan chain for scan test and related circuitry system
US9891282B2 (en) * 2015-12-24 2018-02-13 Intel Corporation Chip fabric interconnect quality on silicon
US10139448B2 (en) * 2016-08-31 2018-11-27 Nxp Usa, Inc. Scan circuitry with IDDQ verification
CN107870832B (zh) * 2016-09-23 2021-06-18 伊姆西Ip控股有限责任公司 基于多维度健康诊断方法的多路径存储设备
KR102712157B1 (ko) * 2016-10-04 2024-09-30 삼성전자주식회사 집적 회로 및 애플리케이션 프로세서
US9733307B1 (en) * 2016-10-20 2017-08-15 International Business Machines Corporation Optimized chain diagnostic fail isolation
KR102769081B1 (ko) 2016-12-22 2025-02-18 삼성전자주식회사 스캔 데이터 컨트롤 장치 및 이를 갖는 전자 시스템
US10247776B2 (en) 2017-02-22 2019-04-02 International Business Machines Corporation Structurally assisted functional test and diagnostics for integrated circuits
US10613142B2 (en) 2017-02-22 2020-04-07 International Business Machines Corporation Non-destructive recirculation test support for integrated circuits
JP6832787B2 (ja) * 2017-04-28 2021-02-24 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置のテスト方法
US10319459B1 (en) * 2017-06-28 2019-06-11 Cadence Design Systems, Inc. Customizable built-in self-test testplans for memory units
US10585142B2 (en) 2017-09-28 2020-03-10 International Business Machines Corporation Functional diagnostics based on dynamic selection of alternate clocking
TWI762538B (zh) * 2017-12-13 2022-05-01 英業達股份有限公司 電路板的電壓腳位導通檢測系統及其方法
WO2020038570A1 (en) * 2018-08-22 2020-02-27 Commsolid Gmbh Extended jtag controller and method for functional reset using the extended jtag controller
WO2020038571A1 (en) * 2018-08-22 2020-02-27 Commsolid Gmbh Extended jtag controller and method for functional debugging using the extended jtag controller
US10817644B2 (en) * 2018-10-19 2020-10-27 Globalfoundries Singapore Pte. Ltd. Circuit and method for design of RF integrated circuits for process control monitoring
US10746792B1 (en) * 2018-11-30 2020-08-18 Amazon Technologies, Inc. Debug mechanisms for a processor circuit
KR102681969B1 (ko) * 2019-01-10 2024-07-08 삼성전자주식회사 논리 회로의 at-speed 테스트를 위한 시스템-온-칩 및 그것의 동작 방법
KR20210014365A (ko) * 2019-07-30 2021-02-09 에스케이하이닉스 주식회사 컨트롤러 및 그 동작 방법
JP7150676B2 (ja) * 2019-09-02 2022-10-11 株式会社東芝 半導体集積回路及びそのテスト方法
US10998075B2 (en) 2019-09-11 2021-05-04 International Business Machines Corporation Built-in self-test for bit-write enabled memory arrays
US10971242B2 (en) * 2019-09-11 2021-04-06 International Business Machines Corporation Sequential error capture during memory test
NL2024200B1 (en) * 2019-11-08 2021-07-20 Jtag Tech B V A method for debugging a printed circuit board.
US11183261B2 (en) * 2020-04-01 2021-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Test device for memory, method for detecting hardware failure in memory device, and test apparatus of memory array
CN112526327B (zh) * 2020-10-28 2022-07-08 深圳市紫光同创电子有限公司 边界扫描测试方法及存储介质
US11513153B2 (en) * 2021-04-19 2022-11-29 Nxp Usa, Inc. System and method for facilitating built-in self-test of system-on-chips
KR20230044680A (ko) * 2021-09-27 2023-04-04 삼성전자주식회사 집적 회로 및 상기 집적 회로를 포함하는 전자 장치
KR20240095164A (ko) * 2021-11-01 2024-06-25 시놉시스, 인크. 임베디드 메모리 투명 시스템-내 빌트-인 셀프-테스트
US11754624B1 (en) 2022-02-24 2023-09-12 Seagate Technology Llc Programmable scan chain debug technique
US12117488B1 (en) * 2023-06-13 2024-10-15 Synopsys, Inc. Multiple clock and clock cycle selection for x-tolerant logic built in self test (XLBIST)
US20260031171A1 (en) * 2024-07-25 2026-01-29 Qualcomm Incorporated Architecture for deterministic memory initialization for automotive electronics
CN121454293A (zh) * 2026-01-06 2026-02-03 深圳市中兴微电子技术有限公司 一种系统级芯片诊断系统、方法、电子设备及程序产品

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5491793A (en) * 1992-07-31 1996-02-13 Fujitsu Limited Debug support in a processor chip
US5828825A (en) * 1993-12-22 1998-10-27 Intel Corporation Method and apparatus for pseudo-direct access to embedded memories of a micro-controller integrated circuit via the IEEE test access port
TW253942B (de) * 1994-01-31 1995-08-11 At & T Corp
US5488688A (en) * 1994-03-30 1996-01-30 Motorola, Inc. Data processor with real-time diagnostic capability
US5544311A (en) * 1995-09-11 1996-08-06 Rockwell International Corporation On-chip debug port
US5724505A (en) * 1996-05-15 1998-03-03 Lucent Technologies Inc. Apparatus and method for real-time program monitoring via a serial interface
EP0826974B1 (de) 1996-08-30 2005-10-19 Texas Instruments Incorporated Vorrichtung zur Prüfung von integrierten Schaltungen
US5828824A (en) * 1996-12-16 1998-10-27 Texas Instruments Incorporated Method for debugging an integrated circuit using extended operating modes
US5881067A (en) * 1997-01-28 1999-03-09 Sun Microsystems, Inc. Flip-flop design and technique for scan chain diagnosis
KR100240662B1 (ko) * 1997-09-25 2000-01-15 윤종용 제이태그에 의한 다이나믹램 테스트장치
JPH11184724A (ja) * 1997-12-18 1999-07-09 Matsushita Electric Ind Co Ltd インサーキットエミュレータ及び半導体集積回路
US6199031B1 (en) * 1998-08-31 2001-03-06 Vlsi Technology, Inc. HDL simulation interface for testing and verifying an ASIC model
US6249893B1 (en) * 1998-10-30 2001-06-19 Advantest Corp. Method and structure for testing embedded cores based system-on-a-chip
US6191603B1 (en) * 1999-01-08 2001-02-20 Agilent Technologies Inc. Modular embedded test system for use in integrated circuits
US6308290B1 (en) * 1999-05-20 2001-10-23 International Business Machines Corporation Look ahead scan chain diagnostic method
US6598192B1 (en) * 2000-02-28 2003-07-22 Motorola, Inc. Method and apparatus for testing an integrated circuit
US6686759B1 (en) * 2000-11-28 2004-02-03 Cadence Design Systems, Inc. Techniques for testing embedded cores in multi-core integrated circuit designs

Also Published As

Publication number Publication date
US7191373B2 (en) 2007-03-13
EP1364436A1 (de) 2003-11-26
EP1364436B1 (de) 2006-05-24
WO2002071567A1 (en) 2002-09-12
DE60211659T2 (de) 2007-04-26
US20070168803A1 (en) 2007-07-19
US20020138801A1 (en) 2002-09-26
US7284175B2 (en) 2007-10-16
EP1364436A4 (de) 2005-02-16
DE60211659D1 (de) 2006-06-29

Similar Documents

Publication Publication Date Title
ATE327587T1 (de) Verfahren und vorrichtung zur diagnose von ausfällen in einer integrierten schaltung unter verwendung von techniken des typs design-for- debug (dfd)
US7934134B2 (en) Method and apparatus for performing logic built-in self-testing of an integrated circuit
US9297855B1 (en) Integrated circuit with increased fault coverage
DE69712236D1 (de) Fehlerdiagnosevorrichtung für CMOS-integrierte Schaltungen und Diagnoseverfahren
US20170097388A1 (en) Lbist debug controller
US6707313B1 (en) Systems and methods for testing integrated circuits
US7921346B2 (en) Verification of array built-in self-test (ABIST) design-for-test/design-for-diagnostics (DFT/DFD)
US20020116675A1 (en) Method and system for determining common failure modes for integrated circuits
CN101071155A (zh) 一种可实现边界扫描多链路测试的装置及方法
US6883115B2 (en) LSI diagnostic system and method of diagnosing LSI
CN107340467B (zh) 测试系统
US7272767B2 (en) Methods and apparatus for incorporating IDDQ testing into logic BIST
Bartenstein Fault distinguishing pattern generation
US8423845B2 (en) On-chip logic to log failures during production testing and enable debugging for failure diagnosis
US6378094B1 (en) Method and system for testing cluster circuits in a boundary scan environment
US7039843B2 (en) Modeling custom scan flops in level sensitive scan design
JP2006105997A (ja) 電子デバイスにスキャンパターンを提供する方法および装置
US20090271671A1 (en) Apparatus and method for improved test controllability and observability of random resistant logic
KR100672082B1 (ko) 이종 코아를 가진 시스템 온 칩에서의 연결선 지연 고장점검 테스트 제어기 및 이를 구비한 시스템 온 칩
CN102565664A (zh) 一种测试覆盖率的评估方法
KR20060095283A (ko) 다중 시스템 클럭 및 이종 코어를 포함하는 시스템 온 칩용연결선 지연 고장 테스트 제어기
Dikic et al. BIST and fault insertion re-use in telecom systems
Day et al. Test methodology for a microprocessor with partial scan
Pateras Embedded diagnosis IP
Lin et al. Accurate diagnosis of multiple faults

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties