ATE344943T1 - Verfahren und vorrichtung für fehlertolerante und flexible test-vektoren-erzeugung - Google Patents

Verfahren und vorrichtung für fehlertolerante und flexible test-vektoren-erzeugung

Info

Publication number
ATE344943T1
ATE344943T1 AT02731860T AT02731860T ATE344943T1 AT E344943 T1 ATE344943 T1 AT E344943T1 AT 02731860 T AT02731860 T AT 02731860T AT 02731860 T AT02731860 T AT 02731860T AT E344943 T1 ATE344943 T1 AT E344943T1
Authority
AT
Austria
Prior art keywords
vector generation
test vector
fault tolerant
flexible test
scan chains
Prior art date
Application number
AT02731860T
Other languages
English (en)
Inventor
Kapila B Udawatta
Anthony Babella
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE344943T1 publication Critical patent/ATE344943T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)
AT02731860T 2001-05-21 2002-05-16 Verfahren und vorrichtung für fehlertolerante und flexible test-vektoren-erzeugung ATE344943T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/862,407 US6738939B2 (en) 2001-05-21 2001-05-21 Method and apparatus for fault tolerant and flexible test signature generator

Publications (1)

Publication Number Publication Date
ATE344943T1 true ATE344943T1 (de) 2006-11-15

Family

ID=25338422

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02731860T ATE344943T1 (de) 2001-05-21 2002-05-16 Verfahren und vorrichtung für fehlertolerante und flexible test-vektoren-erzeugung

Country Status (8)

Country Link
US (1) US6738939B2 (de)
EP (1) EP1393176B1 (de)
CN (1) CN1329833C (de)
AT (1) ATE344943T1 (de)
AU (1) AU2002303801A1 (de)
DE (1) DE60215933T2 (de)
TW (1) TWI230795B (de)
WO (1) WO2002095587A2 (de)

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US6981191B2 (en) * 2001-10-12 2005-12-27 Sun Microsystems, Inc. ASIC logic BIST employing registers seeded with differing primitive polynomials
US6996760B2 (en) * 2001-10-12 2006-02-07 Sun Microsystems ASIC BIST employing stored indications of completion
US7644333B2 (en) * 2001-12-18 2010-01-05 Christopher John Hill Restartable logic BIST controller
US6918074B2 (en) * 2002-06-28 2005-07-12 Intel Corporation At speed testing asynchronous signals
CN1516015B (zh) * 2003-01-09 2010-04-07 华为技术有限公司 多链边界扫描测试系统及多链边界扫描测试方法
US20040139377A1 (en) * 2003-01-13 2004-07-15 International Business Machines Corporation Method and apparatus for compact scan testing
CN100348992C (zh) * 2003-11-19 2007-11-14 华为技术有限公司 一种外围互连线的测试方法
CN100370269C (zh) * 2003-11-19 2008-02-20 华为技术有限公司 一种边界扫描测试控制器及边界扫描测试方法
US6972592B2 (en) * 2003-11-24 2005-12-06 Lsi Logic Corporation Self-timed scan circuit for ASIC fault testing
DE102005046588B4 (de) * 2005-09-28 2016-09-22 Infineon Technologies Ag Vorrichtung und Verfahren zum Test und zur Diagnose digitaler Schaltungen
US7996731B2 (en) 2005-11-02 2011-08-09 Advanced Micro Devices, Inc. Error detection in high-speed asymmetric interfaces
US7415678B2 (en) 2005-11-15 2008-08-19 Synopsys, Inc. Method and apparatus for synthesis of multimode X-tolerant compressor
US20090228751A1 (en) * 2007-05-22 2009-09-10 Tilman Gloekler method for performing logic built-in-self-test cycles on a semiconductor chip and a corresponding semiconductor chip with a test engine
US7882409B2 (en) * 2007-09-21 2011-02-01 Synopsys, Inc. Method and apparatus for synthesis of augmented multimode compactors
US7949921B2 (en) * 2007-09-21 2011-05-24 Synopsys, Inc. Method and apparatus for synthesis of augmented multimode compactors
US8365029B2 (en) * 2007-12-26 2013-01-29 Infineon Technologies Ag Digital circuits and methods for testing a digital circuit
US20090265596A1 (en) * 2008-04-22 2009-10-22 Mediatek Inc. Semiconductor devices, integrated circuit packages and testing methods thereof
US8949493B1 (en) 2010-07-30 2015-02-03 Altera Corporation Configurable multi-lane scrambler for flexible protocol support
US10345369B2 (en) 2012-10-02 2019-07-09 Synopsys, Inc. Augmented power-aware decompressor
EP3153873A1 (de) * 2015-10-07 2017-04-12 Lantiq Beteiligungs-GmbH & Co. KG Test-mustergenerator auf dem chip
US10380303B2 (en) 2015-11-30 2019-08-13 Synopsys, Inc. Power-aware dynamic encoding
US10079070B2 (en) * 2016-10-20 2018-09-18 International Business Machines Corporation Testing content addressable memory and random access memory
US10509072B2 (en) * 2017-03-03 2019-12-17 Mentor Graphics Corporation Test application time reduction using capture-per-cycle test points
US12412014B1 (en) * 2022-08-31 2025-09-09 Cadence Design Systems, Inc. IC chip with IC design modification detection

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US4503537A (en) * 1982-11-08 1985-03-05 International Business Machines Corporation Parallel path self-testing system
US5331643A (en) * 1991-09-04 1994-07-19 International Business Machines Corporation Self-testing logic with embedded arrays
US5329533A (en) * 1991-12-26 1994-07-12 At&T Bell Laboratories Partial-scan built-in self-test technique
EP0642083A1 (de) * 1993-09-04 1995-03-08 International Business Machines Corporation Prüfschaltkreis und Verfahren zum Prüfen von Chipverbindungen
US5991909A (en) 1996-10-15 1999-11-23 Mentor Graphics Corporation Parallel decompressor and related methods and apparatuses
US5790561A (en) * 1997-01-17 1998-08-04 Rockwell International Corporation Internal testability system for microprocessor-based integrated circuit
US5844917A (en) 1997-04-08 1998-12-01 International Business Machines Corporation Method for testing adapter card ASIC using reconfigurable logic
US5930270A (en) 1997-07-23 1999-07-27 International Business Machines Corporation Logic built in self-test diagnostic method
KR100292821B1 (ko) * 1997-09-08 2001-06-15 윤종용 병렬 시그너츄어 압축 회로
US6049901A (en) * 1997-09-16 2000-04-11 Stock; Mary C. Test system for integrated circuits using a single memory for both the parallel and scan modes of testing
US6021514A (en) * 1998-01-22 2000-02-01 International Business Machines Corporation Limited latch linehold capability for LBIST testing
US6442723B1 (en) 1999-05-12 2002-08-27 International Business Machines Corporation Logic built-in self test selective signature generation
US6496503B1 (en) * 1999-06-01 2002-12-17 Intel Corporation Device initialization and operation using directed routing
US6442722B1 (en) 1999-10-29 2002-08-27 Logicvision, Inc. Method and apparatus for testing circuits with multiple clocks
US6557129B1 (en) * 1999-11-23 2003-04-29 Janusz Rajski Method and apparatus for selectively compacting test responses
US6516432B1 (en) * 1999-12-22 2003-02-04 International Business Machines Corporation AC scan diagnostic method

Also Published As

Publication number Publication date
DE60215933D1 (de) 2006-12-21
EP1393176A2 (de) 2004-03-03
WO2002095587A3 (en) 2003-08-28
TWI230795B (en) 2005-04-11
AU2002303801A1 (en) 2002-12-03
CN1529855A (zh) 2004-09-15
US6738939B2 (en) 2004-05-18
EP1393176B1 (de) 2006-11-08
US20020174393A1 (en) 2002-11-21
CN1329833C (zh) 2007-08-01
DE60215933T2 (de) 2007-04-26
WO2002095587A2 (en) 2002-11-28

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