ATE365996T1 - Vorrichtung und verfahren in einer halbleiterschaltung - Google Patents

Vorrichtung und verfahren in einer halbleiterschaltung

Info

Publication number
ATE365996T1
ATE365996T1 AT00986120T AT00986120T ATE365996T1 AT E365996 T1 ATE365996 T1 AT E365996T1 AT 00986120 T AT00986120 T AT 00986120T AT 00986120 T AT00986120 T AT 00986120T AT E365996 T1 ATE365996 T1 AT E365996T1
Authority
AT
Austria
Prior art keywords
delay
semi
circuit
clock signals
circuits
Prior art date
Application number
AT00986120T
Other languages
English (en)
Inventor
Mikael Lindberg
Stefan Davidsson
Ulf Hansson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Application granted granted Critical
Publication of ATE365996T1 publication Critical patent/ATE365996T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Pulse Circuits (AREA)
  • Electronic Switches (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Networks Using Active Elements (AREA)
  • Semiconductor Integrated Circuits (AREA)
AT00986120T 2000-12-05 2000-12-05 Vorrichtung und verfahren in einer halbleiterschaltung ATE365996T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SE2000/002434 WO2002047269A1 (en) 2000-12-05 2000-12-05 Device and method in a semiconductor circuit

Publications (1)

Publication Number Publication Date
ATE365996T1 true ATE365996T1 (de) 2007-07-15

Family

ID=20280286

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00986120T ATE365996T1 (de) 2000-12-05 2000-12-05 Vorrichtung und verfahren in einer halbleiterschaltung

Country Status (6)

Country Link
US (1) US6900683B2 (de)
EP (1) EP1350323B1 (de)
AT (1) ATE365996T1 (de)
AU (1) AU2001222415A1 (de)
DE (1) DE60035373T2 (de)
WO (1) WO2002047269A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0428417D0 (en) * 2004-12-24 2005-02-02 St Microelectronics Res & Dev Programmable digital delay
FR2882207B1 (fr) * 2005-02-15 2007-04-27 Alcatel Sa Dispositif de synchronisation a redondance de signaux d'horloge, pour un equipement d'un reseau de transport synchrone
US8330434B2 (en) * 2008-07-25 2012-12-11 Cirrus Logic, Inc. Power supply that determines energy consumption and outputs a signal indicative of energy consumption
US20120161827A1 (en) * 2010-12-28 2012-06-28 Stmicroelectronics (Canada) Inc. Central lc pll with injection locked ring pll or dell per lane
US20130002297A1 (en) * 2011-06-28 2013-01-03 Texas Instruments, Incorporated Bias temperature instability-resistant circuits
US10026661B2 (en) 2014-09-18 2018-07-17 Samsung Electronics Co., Ltd. Semiconductor device for testing large number of devices and composing method and test method thereof
US9767248B2 (en) * 2014-09-18 2017-09-19 Samsung Electronics, Co., Ltd. Semiconductor having cross coupled structure and layout verification method thereof
US9704862B2 (en) 2014-09-18 2017-07-11 Samsung Electronics Co., Ltd. Semiconductor devices and methods for manufacturing the same
US9811626B2 (en) 2014-09-18 2017-11-07 Samsung Electronics Co., Ltd. Method of designing layout of semiconductor device
US10095825B2 (en) 2014-09-18 2018-10-09 Samsung Electronics Co., Ltd. Computer based system for verifying layout of semiconductor device and layout verify method thereof
JP2017163204A (ja) * 2016-03-07 2017-09-14 ＡＰＲＥＳＩＡ Ｓｙｓｔｅｍｓ株式会社 通信装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06188676A (ja) * 1992-12-17 1994-07-08 Canon Inc 相関器
JP2863684B2 (ja) * 1993-03-09 1999-03-03 株式会社日立製作所 半導体集積回路のディレイ最適化システム、および、ディレイ最適化方法
US5870445A (en) * 1995-12-27 1999-02-09 Raytheon Company Frequency independent clock synchronizer
JPH1069769A (ja) * 1996-08-29 1998-03-10 Fujitsu Ltd 半導体集積回路
JP3739525B2 (ja) * 1996-12-27 2006-01-25 富士通株式会社 可変遅延回路及び半導体集積回路装置
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
US6157226A (en) * 1997-05-23 2000-12-05 Mitsubishi Denki Kabushiki Kaisha Clock generator
US6011732A (en) * 1997-08-20 2000-01-04 Micron Technology, Inc. Synchronous clock generator including a compound delay-locked loop
KR100261216B1 (ko) * 1997-11-21 2000-07-01 윤종용 프로그래머블 지연라인
KR100269316B1 (ko) * 1997-12-02 2000-10-16 윤종용 동기지연회로가결합된지연동기루프(dll)및위상동기루프(pll)
US5994938A (en) * 1998-01-30 1999-11-30 Credence Systems Corporation Self-calibrating programmable phase shifter
US6369624B1 (en) * 1998-11-03 2002-04-09 Altera Corporation Programmable phase shift circuitry
US6100735A (en) * 1998-11-19 2000-08-08 Centillium Communications, Inc. Segmented dual delay-locked loop for precise variable-phase clock generation
US6285226B1 (en) * 1999-10-25 2001-09-04 Xilinx, Inc. Duty cycle correction circuit and method
US6229358B1 (en) * 1999-12-15 2001-05-08 International Business Machines Corporation Delayed matching signal generator and frequency multiplier using scaled delay networks

Also Published As

Publication number Publication date
DE60035373T2 (de) 2008-03-13
US6900683B2 (en) 2005-05-31
AU2001222415A1 (en) 2002-06-18
US20040012429A1 (en) 2004-01-22
DE60035373D1 (de) 2007-08-09
EP1350323A1 (de) 2003-10-08
WO2002047269A1 (en) 2002-06-13
EP1350323B1 (de) 2007-06-27

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Legal Events

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