ATE368285T1 - Verfahren und vorrichtung zum einstellen und kompensieren der leselatenz in einem hochgeschwindigkeits-dram - Google Patents

Verfahren und vorrichtung zum einstellen und kompensieren der leselatenz in einem hochgeschwindigkeits-dram

Info

Publication number
ATE368285T1
ATE368285T1 AT03791767T AT03791767T ATE368285T1 AT E368285 T1 ATE368285 T1 AT E368285T1 AT 03791767 T AT03791767 T AT 03791767T AT 03791767 T AT03791767 T AT 03791767T AT E368285 T1 ATE368285 T1 AT E368285T1
Authority
AT
Austria
Prior art keywords
read
clock signal
compensating
adjusting
signal
Prior art date
Application number
AT03791767T
Other languages
English (en)
Inventor
Brent Keeth
Brian Johnson
Feng Lin
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE368285T1 publication Critical patent/ATE368285T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Memory System (AREA)
AT03791767T 2002-08-29 2003-08-27 Verfahren und vorrichtung zum einstellen und kompensieren der leselatenz in einem hochgeschwindigkeits-dram ATE368285T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/230,221 US6687185B1 (en) 2002-08-29 2002-08-29 Method and apparatus for setting and compensating read latency in a high speed DRAM

Publications (1)

Publication Number Publication Date
ATE368285T1 true ATE368285T1 (de) 2007-08-15

Family

ID=30443782

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03791767T ATE368285T1 (de) 2002-08-29 2003-08-27 Verfahren und vorrichtung zum einstellen und kompensieren der leselatenz in einem hochgeschwindigkeits-dram

Country Status (10)

Country Link
US (1) US6687185B1 (de)
EP (1) EP1537582B1 (de)
JP (1) JP4322209B2 (de)
KR (1) KR100607764B1 (de)
CN (1) CN100446116C (de)
AT (1) ATE368285T1 (de)
AU (1) AU2003260069A1 (de)
DE (1) DE60315165T2 (de)
TW (1) TWI239534B (de)
WO (1) WO2004021352A1 (de)

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US6930949B2 (en) * 2002-08-26 2005-08-16 Micron Technology, Inc. Power savings in active standby mode
US6762974B1 (en) * 2003-03-18 2004-07-13 Micron Technology, Inc. Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM
US7177224B2 (en) * 2003-05-21 2007-02-13 Micron Technology, Inc. Controlling multiple signal polarity in a semiconductor device
US20050190193A1 (en) * 2004-03-01 2005-09-01 Freker David E. Apparatus and a method to adjust signal timing on a memory interface
EP1735794B1 (de) * 2004-03-31 2011-04-27 Micron Technology, Inc. Rekonstruktion des signal-timing in integrierten schaltungen
DE102004015868A1 (de) 2004-03-31 2005-10-27 Micron Technology, Inc. Rekonstruktion der Signalzeitgebung in integrierten Schaltungen
US8224574B2 (en) * 2004-05-12 2012-07-17 Northrop Grumman Guidance And Electronics Company, Inc. System for multiple navigation components
US7065001B2 (en) * 2004-08-04 2006-06-20 Micron Technology, Inc. Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
US7660187B2 (en) * 2004-08-04 2010-02-09 Micron Technology, Inc. Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
KR100625296B1 (ko) 2004-12-30 2006-09-19 주식회사 하이닉스반도체 고주파수 동작을 위한 동기식 반도체 장치의 레이턴시제어장치 및 그 제어방법
US7272054B2 (en) * 2005-07-08 2007-09-18 Micron Technology, Inc. Time domain bridging circuitry for use in determining output enable timing
US7526704B2 (en) * 2005-08-23 2009-04-28 Micron Technology, Inc. Testing system and method allowing adjustment of signal transmit timing
KR100665232B1 (ko) * 2005-12-26 2007-01-09 삼성전자주식회사 동기식 반도체 메모리 장치
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CN101416437A (zh) * 2006-04-05 2009-04-22 松下电器产业株式会社 可移动存储装置、相位同步方法、相位同步程序、其记录介质及主机终端
TWI305651B (en) * 2006-09-11 2009-01-21 Nanya Technology Corp Latency counter having frequency detector and latency counting method thereof
CN100543871C (zh) * 2006-09-20 2009-09-23 南亚科技股份有限公司 具有频率检测器的延迟计数器及其延迟计数方法
JP2008108417A (ja) * 2006-10-23 2008-05-08 Hynix Semiconductor Inc 低電力ｄｒａｍ及びその駆動方法
US7716510B2 (en) * 2006-12-19 2010-05-11 Micron Technology, Inc. Timing synchronization circuit with loop counter
KR100866958B1 (ko) 2007-02-08 2008-11-05 삼성전자주식회사 고속 ｄｒａｍ의 정확한 독출 레이턴시를 제어하는 방법 및장치
US7656745B2 (en) * 2007-03-15 2010-02-02 Micron Technology, Inc. Circuit, system and method for controlling read latency
JP5687412B2 (ja) * 2009-01-16 2015-03-18 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置及びそのリード待ち時間調整方法、メモリシステム、並びに半導体装置
US7969813B2 (en) 2009-04-01 2011-06-28 Micron Technology, Inc. Write command and write data timing circuit and methods for timing the same
US8117483B2 (en) * 2009-05-13 2012-02-14 Freescale Semiconductor, Inc. Method to calibrate start values for write leveling in a memory system
KR101027686B1 (ko) * 2009-07-30 2011-04-12 주식회사 하이닉스반도체 반도체 메모리 장치
US8984320B2 (en) 2011-03-29 2015-03-17 Micron Technology, Inc. Command paths, apparatuses and methods for providing a command to a data block
US8509011B2 (en) 2011-04-25 2013-08-13 Micron Technology, Inc. Command paths, apparatuses, memories, and methods for providing internal commands to a data path
US8901938B2 (en) * 2012-02-01 2014-12-02 Nanya Technology Corp. Delay line scheme with no exit tree
US8552776B2 (en) 2012-02-01 2013-10-08 Micron Technology, Inc. Apparatuses and methods for altering a forward path delay of a signal path
US9166579B2 (en) 2012-06-01 2015-10-20 Micron Technology, Inc. Methods and apparatuses for shifting data signals to match command signal delay
US9054675B2 (en) 2012-06-22 2015-06-09 Micron Technology, Inc. Apparatuses and methods for adjusting a minimum forward path delay of a signal path
US9047237B2 (en) * 2012-08-03 2015-06-02 Cypress Semiconductor Corporation Power savings apparatus and method for memory device using delay locked loop
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KR102011135B1 (ko) * 2012-12-11 2019-08-14 삼성전자주식회사 모바일 장치 및 그것의 스왑을 통한 데이터 관리 방법
US9734097B2 (en) 2013-03-15 2017-08-15 Micron Technology, Inc. Apparatuses and methods for variable latency memory operations
US9727493B2 (en) 2013-08-14 2017-08-08 Micron Technology, Inc. Apparatuses and methods for providing data to a configurable storage area
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US9508417B2 (en) 2014-02-20 2016-11-29 Micron Technology, Inc. Methods and apparatuses for controlling timing paths and latency based on a loop delay
US9530473B2 (en) 2014-05-22 2016-12-27 Micron Technology, Inc. Apparatuses and methods for timing provision of a command to input circuitry
US9531363B2 (en) 2015-04-28 2016-12-27 Micron Technology, Inc. Methods and apparatuses including command latency control circuit
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WO2017015222A1 (en) * 2015-07-20 2017-01-26 Lattice Semiconductor Corporation Low-speed bus time stamp methods and circuitry
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US9601170B1 (en) 2016-04-26 2017-03-21 Micron Technology, Inc. Apparatuses and methods for adjusting a delay of a command signal path
US9997220B2 (en) 2016-08-22 2018-06-12 Micron Technology, Inc. Apparatuses and methods for adjusting delay of command signal path
US10224938B2 (en) 2017-07-26 2019-03-05 Micron Technology, Inc. Apparatuses and methods for indirectly detecting phase variations
CN110018789B (zh) * 2019-03-26 2022-03-25 记忆科技(深圳)有限公司 动态适配NAND的Tr和Tprom时间的方法、装置及存储介质
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Also Published As

Publication number Publication date
KR100607764B1 (ko) 2006-08-01
US6687185B1 (en) 2004-02-03
TW200418045A (en) 2004-09-16
AU2003260069A1 (en) 2004-03-19
JP4322209B2 (ja) 2009-08-26
KR20050086411A (ko) 2005-08-30
JP2006514760A (ja) 2006-05-11
EP1537582B1 (de) 2007-07-25
TWI239534B (en) 2005-09-11
CN1695199A (zh) 2005-11-09
CN100446116C (zh) 2008-12-24
EP1537582A1 (de) 2005-06-08
DE60315165T2 (de) 2008-04-17
WO2004021352A1 (en) 2004-03-11
DE60315165D1 (de) 2007-09-06

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