ATE371896T1 - Datenverarbeitungsschaltung mit gemultiplextem speicher - Google Patents

Datenverarbeitungsschaltung mit gemultiplextem speicher

Info

Publication number
ATE371896T1
ATE371896T1 AT04736433T AT04736433T ATE371896T1 AT E371896 T1 ATE371896 T1 AT E371896T1 AT 04736433 T AT04736433 T AT 04736433T AT 04736433 T AT04736433 T AT 04736433T AT E371896 T1 ATE371896 T1 AT E371896T1
Authority
AT
Austria
Prior art keywords
memory
data processing
access request
processing circuits
processing circuit
Prior art date
Application number
AT04736433T
Other languages
English (en)
Inventor
Jozef Kessels
Ivan Andrejic
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE371896T1 publication Critical patent/ATE371896T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
  • Dram (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Communication Control (AREA)
  • Bus Control (AREA)
AT04736433T 2003-06-16 2004-06-09 Datenverarbeitungsschaltung mit gemultiplextem speicher ATE371896T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03101749 2003-06-16

Publications (1)

Publication Number Publication Date
ATE371896T1 true ATE371896T1 (de) 2007-09-15

Family

ID=33547717

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04736433T ATE371896T1 (de) 2003-06-16 2004-06-09 Datenverarbeitungsschaltung mit gemultiplextem speicher

Country Status (9)

Country Link
US (3) US7487300B2 (de)
EP (1) EP1639478B1 (de)
JP (1) JP2006527878A (de)
KR (1) KR20060017876A (de)
CN (1) CN100483374C (de)
AT (1) ATE371896T1 (de)
DE (1) DE602004008628T2 (de)
TW (1) TWI396977B (de)
WO (1) WO2004111860A2 (de)

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ATE442623T1 (de) * 2004-01-13 2009-09-15 Koninkl Philips Electronics Nv Elektronsiche schaltung mit einer fifo-pipeline
US7386743B2 (en) * 2005-06-09 2008-06-10 International Business Machines Corporation Power-managed server and method for managing power consumption
US7509506B2 (en) * 2005-06-09 2009-03-24 International Business Machines Corporation Hierarchical system and method for managing power usage among server data processing systems
US7421599B2 (en) * 2005-06-09 2008-09-02 International Business Machines Corporation Power management server and method for managing power consumption
US7467311B2 (en) * 2005-06-09 2008-12-16 International Business Machines Corporation Distributed system and method for managing power usage among server data processing systems
US7590788B2 (en) * 2007-10-29 2009-09-15 Intel Corporation Controlling transmission on an asynchronous bus
FR2936620B1 (fr) * 2008-10-01 2010-10-22 Ingenico Sa Terminal de paiement electronique a affichage ameliore
US8805590B2 (en) * 2009-12-24 2014-08-12 International Business Machines Corporation Fan speed control of rack devices where sum of device airflows is greater than maximum airflow of rack
US9176908B2 (en) 2010-02-23 2015-11-03 Rambus Inc. Time multiplexing at different rates to access different memory types
WO2011158500A1 (ja) * 2010-06-17 2011-12-22 国立大学法人 奈良先端科学技術大学院大学 スキャン非同期記憶素子およびそれを備えた半導体集積回路ならびにその設計方法およびテストパターン生成方法
KR101949671B1 (ko) 2012-06-28 2019-04-25 삼성전자 주식회사 라이프 싸이클을 증가시킬 수 있는 저장 장치 및 그 동작 방법
CN104346285B (zh) 2013-08-06 2018-05-11 华为技术有限公司 内存访问处理方法、装置及系统
CN104731550B (zh) * 2015-03-12 2017-10-17 电子科技大学 一种基于单fifo的双倍时钟双向数字延迟方法
US10686539B2 (en) * 2015-05-29 2020-06-16 Avago Technologies International Sales Pte. Limited Flexible debug observation point insertion in pipeline designs
CN118069218A (zh) * 2017-09-12 2024-05-24 恩倍科微公司 极低功率微控制器系统
CN109189829B (zh) * 2018-08-20 2019-07-26 太平洋电信股份有限公司 基于大数据的信息安全系统和方法

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JPS6116086A (ja) * 1984-06-30 1986-01-24 Toshiba Corp メモリ制御方式
JPH01315857A (ja) * 1988-06-16 1989-12-20 Oki Electric Ind Co Ltd 共有メモリアクセス方式
JPH0279088A (ja) * 1988-09-16 1990-03-19 Hitachi Ltd 表示メモリアクセス方法
US5202973A (en) * 1990-06-29 1993-04-13 Digital Equipment Corporation Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus
JP3523286B2 (ja) * 1993-03-12 2004-04-26 株式会社日立製作所 順次データ転送型メモリ及び順次データ転送型メモリを用いたコンピュータシステム
EP0752174A1 (de) * 1995-01-25 1997-01-08 Advanced Micro Devices, Inc. Schnelle verriegelungsschaltung, die mehreren übertragungsgattern enthält und pipeline-mikroprozessor der dieselbe verwendet
US5684422A (en) 1995-01-25 1997-11-04 Advanced Micro Devices, Inc. Pipelined microprocessor including a high speed single-clock latch circuit
JPH08328941A (ja) * 1995-05-31 1996-12-13 Nec Corp メモリアクセス制御回路
FR2737636B1 (fr) * 1995-08-03 1997-10-17 Sgs Thomson Microelectronics Dispositif de transfert de donnees binaires entre un multiplex par division du temps et une memoire
JP3444154B2 (ja) * 1997-09-17 2003-09-08 日本電気株式会社 メモリアクセス制御回路
US6175905B1 (en) * 1998-07-30 2001-01-16 Micron Technology, Inc. Method and system for bypassing pipelines in a pipelined memory command generator
US6205524B1 (en) * 1998-09-16 2001-03-20 Neomagic Corp. Multimedia arbiter and method using fixed round-robin slots for real-time agents and a timed priority slot for non-real-time agents
TW522399B (en) * 1999-12-08 2003-03-01 Hitachi Ltd Semiconductor device
US6412049B1 (en) * 1999-12-16 2002-06-25 Intel Corporation Method for minimizing CPU memory latency while transferring streaming data
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US6785793B2 (en) * 2001-09-27 2004-08-31 Intel Corporation Method and apparatus for memory access scheduling to reduce memory access latency
US7114051B2 (en) * 2002-06-01 2006-09-26 Solid State System Co., Ltd. Method for partitioning memory mass storage device
US20040003194A1 (en) * 2002-06-26 2004-01-01 Amit Bodas Method and apparatus for adjusting DRAM signal timings

Also Published As

Publication number Publication date
KR20060017876A (ko) 2006-02-27
TW200502769A (en) 2005-01-16
US8473706B2 (en) 2013-06-25
CN100483374C (zh) 2009-04-29
EP1639478B1 (de) 2007-08-29
US7487300B2 (en) 2009-02-03
JP2006527878A (ja) 2006-12-07
TWI396977B (zh) 2013-05-21
WO2004111860A2 (en) 2004-12-23
US8190829B2 (en) 2012-05-29
CN1806234A (zh) 2006-07-19
DE602004008628D1 (de) 2007-10-11
EP1639478A2 (de) 2006-03-29
US20120303921A1 (en) 2012-11-29
US20090106520A1 (en) 2009-04-23
DE602004008628T2 (de) 2008-06-05
WO2004111860A3 (en) 2005-02-10
US20060168416A1 (en) 2006-07-27

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