ATE372550T1 - Cache-crossbar-arbitrierung - Google Patents
Cache-crossbar-arbitrierungInfo
- Publication number
- ATE372550T1 ATE372550T1 AT04779817T AT04779817T ATE372550T1 AT E372550 T1 ATE372550 T1 AT E372550T1 AT 04779817 T AT04779817 T AT 04779817T AT 04779817 T AT04779817 T AT 04779817T AT E372550 T1 ATE372550 T1 AT E372550T1
- Authority
- AT
- Austria
- Prior art keywords
- processing cores
- processor chip
- arbiter
- crossbar
- outputs
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1657—Access to multiple memories
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
- G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Multimedia (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Bus Control (AREA)
- Advance Control (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US49660203P | 2003-08-19 | 2003-08-19 | |
| US10/855,060 US7133950B2 (en) | 2003-08-19 | 2004-05-26 | Request arbitration in multi-core processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE372550T1 true ATE372550T1 (de) | 2007-09-15 |
Family
ID=34221419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT04779817T ATE372550T1 (de) | 2003-08-19 | 2004-07-30 | Cache-crossbar-arbitrierung |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7133950B2 (de) |
| EP (1) | EP1656615B1 (de) |
| AT (1) | ATE372550T1 (de) |
| DE (1) | DE602004008783T2 (de) |
| TW (1) | TW200516399A (de) |
| WO (1) | WO2005020079A2 (de) |
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| US7925975B2 (en) * | 2006-03-10 | 2011-04-12 | Microsoft Corporation | Searching for commands to execute in applications |
| WO2007143278A2 (en) | 2006-04-12 | 2007-12-13 | Soft Machines, Inc. | Apparatus and method for processing an instruction matrix specifying parallel and dependent operations |
| EP2523101B1 (de) | 2006-11-14 | 2014-06-04 | Soft Machines, Inc. | Vorrichtung und Verfahren zum Verarbeiten von komplexen Anweisungsformaten in einer Multi-Thread-Architektur, die verschiedene Kontextschaltungsmodi und Visualisierungsschemen unterstützt |
| US7996632B1 (en) | 2006-12-22 | 2011-08-09 | Oracle America, Inc. | Device for misaligned atomics for a highly-threaded x86 processor |
| US7865647B2 (en) * | 2006-12-27 | 2011-01-04 | Mips Technologies, Inc. | Efficient resource arbitration |
| US7937535B2 (en) * | 2007-02-22 | 2011-05-03 | Arm Limited | Managing cache coherency in a data processing apparatus |
| US7814253B2 (en) * | 2007-04-16 | 2010-10-12 | Nvidia Corporation | Resource arbiter |
| US7673087B1 (en) * | 2008-03-27 | 2010-03-02 | Xilinx, Inc. | Arbitration for an embedded processor block core in an integrated circuit |
| EP2551776B1 (de) * | 2010-03-25 | 2017-11-22 | Fujitsu Limited | Multikernprozessorsystem, steuerprogramm und steuerverfahren |
| CN103250131B (zh) | 2010-09-17 | 2015-12-16 | 索夫特机械公司 | 包括用于早期远分支预测的影子缓存的单周期多分支预测 |
| CN103547993B (zh) | 2011-03-25 | 2018-06-26 | 英特尔公司 | 通过使用由可分割引擎实例化的虚拟核来执行指令序列代码块 |
| CN108376097B (zh) | 2011-03-25 | 2022-04-15 | 英特尔公司 | 用于通过使用由可分割引擎实例化的虚拟核来支持代码块执行的寄存器文件段 |
| WO2012135050A2 (en) | 2011-03-25 | 2012-10-04 | Soft Machines, Inc. | Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines |
| US9940134B2 (en) | 2011-05-20 | 2018-04-10 | Intel Corporation | Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines |
| WO2012162189A1 (en) | 2011-05-20 | 2012-11-29 | Soft Machines, Inc. | An interconnect structure to support the execution of instruction sequences by a plurality of engines |
| US9330002B2 (en) * | 2011-10-31 | 2016-05-03 | Cavium, Inc. | Multi-core interconnect in a network processor |
| US20150039859A1 (en) | 2011-11-22 | 2015-02-05 | Soft Machines, Inc. | Microprocessor accelerated code optimizer |
| KR101703401B1 (ko) | 2011-11-22 | 2017-02-06 | 소프트 머신즈, 인크. | 다중 엔진 마이크로프로세서용 가속 코드 최적화기 |
| US8930674B2 (en) | 2012-03-07 | 2015-01-06 | Soft Machines, Inc. | Systems and methods for accessing a unified translation lookaside buffer |
| US9740612B2 (en) | 2012-07-30 | 2017-08-22 | Intel Corporation | Systems and methods for maintaining the coherency of a store coalescing cache and a load cache |
| US9430410B2 (en) | 2012-07-30 | 2016-08-30 | Soft Machines, Inc. | Systems and methods for supporting a plurality of load accesses of a cache in a single cycle |
| US9710399B2 (en) | 2012-07-30 | 2017-07-18 | Intel Corporation | Systems and methods for flushing a cache with modified data |
| US9916253B2 (en) | 2012-07-30 | 2018-03-13 | Intel Corporation | Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput |
| WO2014022115A1 (en) * | 2012-07-30 | 2014-02-06 | Soft Machines, Inc. | Systems and methods for supporting a plurality of load accesses of a cache in a single cycle |
| US9229873B2 (en) | 2012-07-30 | 2016-01-05 | Soft Machines, Inc. | Systems and methods for supporting a plurality of load and store accesses of a cache |
| US9678882B2 (en) | 2012-10-11 | 2017-06-13 | Intel Corporation | Systems and methods for non-blocking implementation of cache flush instructions |
| US9405711B2 (en) * | 2013-01-09 | 2016-08-02 | International Business Machines Corporation | On-chip traffic prioritization in memory |
| US9891924B2 (en) | 2013-03-15 | 2018-02-13 | Intel Corporation | Method for implementing a reduced size register view data structure in a microprocessor |
| US9811342B2 (en) | 2013-03-15 | 2017-11-07 | Intel Corporation | Method for performing dual dispatch of blocks and half blocks |
| US10140138B2 (en) | 2013-03-15 | 2018-11-27 | Intel Corporation | Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation |
| WO2014150971A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for dependency broadcasting through a block organized source view data structure |
| US9569216B2 (en) | 2013-03-15 | 2017-02-14 | Soft Machines, Inc. | Method for populating a source view data structure by using register template snapshots |
| WO2014150991A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for implementing a reduced size register view data structure in a microprocessor |
| KR101708591B1 (ko) | 2013-03-15 | 2017-02-20 | 소프트 머신즈, 인크. | 블록들로 그룹화된 멀티스레드 명령어들을 실행하기 위한 방법 |
| US9886279B2 (en) | 2013-03-15 | 2018-02-06 | Intel Corporation | Method for populating and instruction view data structure by using register template snapshots |
| US9904625B2 (en) | 2013-03-15 | 2018-02-27 | Intel Corporation | Methods, systems and apparatus for predicting the way of a set associative cache |
| US10275255B2 (en) | 2013-03-15 | 2019-04-30 | Intel Corporation | Method for dependency broadcasting through a source organized source view data structure |
| WO2014150806A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for populating register view data structure by using register template snapshots |
| KR102083390B1 (ko) | 2013-03-15 | 2020-03-02 | 인텔 코포레이션 | 네이티브 분산된 플래그 아키텍처를 이용하여 게스트 중앙 플래그 아키텍처를 에뮬레이션하는 방법 |
| US9678906B2 (en) * | 2014-03-26 | 2017-06-13 | International Business Machines Corporation | Oldest link first arbitration between links grouped as single arbitration elements |
| US20150331608A1 (en) * | 2014-05-16 | 2015-11-19 | Samsung Electronics Co., Ltd. | Electronic system with transactions and method of operation thereof |
| US11520560B2 (en) | 2018-12-31 | 2022-12-06 | Kevin D. Howard | Computer processing and outcome prediction systems and methods |
| US11687328B2 (en) | 2021-08-12 | 2023-06-27 | C Squared Ip Holdings Llc | Method and system for software enhancement and management |
| US11861336B2 (en) | 2021-08-12 | 2024-01-02 | C Squared Ip Holdings Llc | Software systems and methods for multiple TALP family enhancement and management |
| US12099444B2 (en) * | 2022-01-21 | 2024-09-24 | Centaur Technology, Inc. | Cat aware loads and software prefetches |
| US12307528B2 (en) | 2022-09-20 | 2025-05-20 | Diligence Fund Distributors Inc. | Software systems and methods to automatically correlate subject matter items and provider data across multiple platforms |
| US12411671B1 (en) | 2025-04-04 | 2025-09-09 | Kevin D. Howard | Software systems and methods for advanced output-affecting linear pathways |
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| JPS62230718A (ja) | 1986-03-31 | 1987-10-09 | Nitto Electric Ind Co Ltd | 皮膚貼付用ゲル組成物 |
| JPS6473444A (en) * | 1987-09-14 | 1989-03-17 | Mitsubishi Electric Corp | Arbitration circuit |
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| JP3034408B2 (ja) * | 1993-09-30 | 2000-04-17 | 株式会社東芝 | シフト回路及び可変長符号復号器 |
| US5526510A (en) * | 1994-02-28 | 1996-06-11 | Intel Corporation | Method and apparatus for implementing a single clock cycle line replacement in a data cache unit |
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| US6529990B1 (en) * | 1999-11-08 | 2003-03-04 | International Business Machines Corporation | Method and apparatus to eliminate failed snoops of transactions caused by bus timing conflicts in a distributed symmetric multiprocessor system |
| US6532509B1 (en) * | 1999-12-22 | 2003-03-11 | Intel Corporation | Arbitrating command requests in a parallel multi-threaded processing system |
| US6647449B1 (en) * | 2000-10-05 | 2003-11-11 | Hewlett-Packard Development Company, L.P. | System, method and circuit for performing round robin arbitration |
| US6754775B2 (en) * | 2001-06-06 | 2004-06-22 | Sun Microsystems, Inc. | Method and apparatus for facilitating flow control during accesses to cache memory |
| US7248585B2 (en) | 2001-10-22 | 2007-07-24 | Sun Microsystems, Inc. | Method and apparatus for a packet classifier |
-
2004
- 2004-05-26 US US10/855,060 patent/US7133950B2/en not_active Expired - Lifetime
- 2004-07-30 DE DE602004008783T patent/DE602004008783T2/de not_active Expired - Lifetime
- 2004-07-30 WO PCT/US2004/024869 patent/WO2005020079A2/en not_active Ceased
- 2004-07-30 EP EP04779817A patent/EP1656615B1/de not_active Expired - Lifetime
- 2004-07-30 AT AT04779817T patent/ATE372550T1/de not_active IP Right Cessation
- 2004-08-11 TW TW093124041A patent/TW200516399A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| EP1656615A2 (de) | 2006-05-17 |
| WO2005020079A2 (en) | 2005-03-03 |
| DE602004008783D1 (de) | 2007-10-18 |
| US7133950B2 (en) | 2006-11-07 |
| DE602004008783T2 (de) | 2008-06-12 |
| WO2005020079A3 (en) | 2006-01-12 |
| TW200516399A (en) | 2005-05-16 |
| US20050060457A1 (en) | 2005-03-17 |
| EP1656615B1 (de) | 2007-09-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |