ATE550716T1 - Crossbar-architektur mit mehrkern-mehrthread- prozessoren - Google Patents

Crossbar-architektur mit mehrkern-mehrthread- prozessoren

Info

Publication number
ATE550716T1
ATE550716T1 AT04779701T AT04779701T ATE550716T1 AT E550716 T1 ATE550716 T1 AT E550716T1 AT 04779701 T AT04779701 T AT 04779701T AT 04779701 T AT04779701 T AT 04779701T AT E550716 T1 ATE550716 T1 AT E550716T1
Authority
AT
Austria
Prior art keywords
processing cores
crossbar
processor chip
core
cache bank
Prior art date
Application number
AT04779701T
Other languages
English (en)
Inventor
Kunle Olukotun
Original Assignee
Oracle America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oracle America Inc filed Critical Oracle America Inc
Application granted granted Critical
Publication of ATE550716T1 publication Critical patent/ATE550716T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
AT04779701T 2003-08-19 2004-07-30 Crossbar-architektur mit mehrkern-mehrthread- prozessoren ATE550716T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US49660203P 2003-08-19 2003-08-19
US10/855,694 US8463996B2 (en) 2003-08-19 2004-05-26 Multi-core multi-thread processor crossbar architecture
PCT/US2004/024726 WO2005020066A2 (en) 2003-08-19 2004-07-30 Multi-core multi-thread processor crossbar architecture

Publications (1)

Publication Number Publication Date
ATE550716T1 true ATE550716T1 (de) 2012-04-15

Family

ID=34221420

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04779701T ATE550716T1 (de) 2003-08-19 2004-07-30 Crossbar-architektur mit mehrkern-mehrthread- prozessoren

Country Status (5)

Country Link
US (1) US8463996B2 (de)
EP (1) EP1660991B1 (de)
AT (1) ATE550716T1 (de)
TW (1) TWI270787B (de)
WO (1) WO2005020066A2 (de)

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GB0519981D0 (en) 2005-09-30 2005-11-09 Ignios Ltd Scheduling in a multicore architecture
US8255610B2 (en) 2009-02-13 2012-08-28 The Regents Of The University Of Michigan Crossbar circuitry for applying a pre-selection prior to arbitration between transmission requests and method of operation of such crossbar circuitry
US8230152B2 (en) * 2009-02-13 2012-07-24 The Regents Of The University Of Michigan Crossbar circuitry and method of operation of such crossbar circuitry
US9514074B2 (en) 2009-02-13 2016-12-06 The Regents Of The University Of Michigan Single cycle arbitration within an interconnect
US8549207B2 (en) 2009-02-13 2013-10-01 The Regents Of The University Of Michigan Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry
US9286256B2 (en) * 2009-09-28 2016-03-15 Nvidia Corporation Sharing data crossbar for reads and writes in a data cache
US8832415B2 (en) * 2010-01-08 2014-09-09 International Business Machines Corporation Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests
US8380724B2 (en) * 2009-11-24 2013-02-19 Microsoft Corporation Grouping mechanism for multiple processor core execution
US9081501B2 (en) * 2010-01-08 2015-07-14 International Business Machines Corporation Multi-petascale highly efficient parallel supercomputer
US8751720B2 (en) 2010-11-08 2014-06-10 Moon J. Kim Computationally-networked unified data bus
US8902625B2 (en) * 2011-11-22 2014-12-02 Marvell World Trade Ltd. Layouts for memory and logic circuits in a system-on-chip
KR101867960B1 (ko) * 2012-01-05 2018-06-18 삼성전자주식회사 매니 코어 시스템을 위한 운영체제 동적 재구성 장치 및 방법
GB2580165B (en) * 2018-12-21 2021-02-24 Graphcore Ltd Data exchange in a computer with predetermined delay
KR102710630B1 (ko) * 2019-08-19 2024-09-27 에스케이하이닉스 주식회사 페이지 버퍼를 구비하는 반도체 메모리 장치

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US4627050A (en) * 1984-05-22 1986-12-02 Rolm Corporation Time division multiplexed computerized branch exchange
US5526510A (en) * 1994-02-28 1996-06-11 Intel Corporation Method and apparatus for implementing a single clock cycle line replacement in a data cache unit
GB2311882B (en) * 1996-04-04 2000-08-09 Videologic Ltd A data processing management system
US6209020B1 (en) * 1996-09-20 2001-03-27 Nortel Networks Limited Distributed pipeline memory architecture for a computer system with even and odd pids
US5895487A (en) * 1996-11-13 1999-04-20 International Business Machines Corporation Integrated processing and L2 DRAM cache
US6085276A (en) * 1997-10-24 2000-07-04 Compaq Computers Corporation Multi-processor computer system having a data switch with simultaneous insertion buffers for eliminating arbitration interdependencies
US6480927B1 (en) * 1997-12-31 2002-11-12 Unisys Corporation High-performance modular memory system with crossbar connections
US6065085A (en) * 1998-01-27 2000-05-16 Lsi Logic Corporation Bus bridge architecture for a data processing system capable of sharing processing load among a plurality of devices
US6477623B2 (en) * 1998-10-23 2002-11-05 Micron Technology, Inc. Method for providing graphics controller embedded in a core logic unit
JP3721283B2 (ja) * 1999-06-03 2005-11-30 株式会社日立製作所 主記憶共有型マルチプロセッサシステム
US6553460B1 (en) * 1999-10-01 2003-04-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
PL357822A1 (pl) * 2000-04-14 2004-07-26 Mars Incorporated Kompozycje i sposoby polepszania stanu zdrowia układu naczyniowego
US6557070B1 (en) * 2000-06-22 2003-04-29 International Business Machines Corporation Scalable crossbar switch
US6754775B2 (en) * 2001-06-06 2004-06-22 Sun Microsystems, Inc. Method and apparatus for facilitating flow control during accesses to cache memory
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US6912612B2 (en) * 2002-02-25 2005-06-28 Intel Corporation Shared bypass bus structure
US6931489B2 (en) * 2002-08-12 2005-08-16 Hewlett-Packard Development Company, L.P. Apparatus and methods for sharing cache among processors

Also Published As

Publication number Publication date
EP1660991A2 (de) 2006-05-31
TW200511035A (en) 2005-03-16
US20060136605A1 (en) 2006-06-22
EP1660991B1 (de) 2012-03-21
TWI270787B (en) 2007-01-11
US8463996B2 (en) 2013-06-11
WO2005020066A3 (en) 2006-04-06
WO2005020066A2 (en) 2005-03-03

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