ATE373862T1 - Steuergate- und wortleitungs- spannungserhöhungsverfahren für zwilling-monos- zellenspeichern - Google Patents

Steuergate- und wortleitungs- spannungserhöhungsverfahren für zwilling-monos- zellenspeichern

Info

Publication number
ATE373862T1
ATE373862T1 AT02368073T AT02368073T ATE373862T1 AT E373862 T1 ATE373862 T1 AT E373862T1 AT 02368073 T AT02368073 T AT 02368073T AT 02368073 T AT02368073 T AT 02368073T AT E373862 T1 ATE373862 T1 AT E373862T1
Authority
AT
Austria
Prior art keywords
voltage
selected word
control gate
word line
control gates
Prior art date
Application number
AT02368073T
Other languages
English (en)
Inventor
Nori Ogura
Seiki Ogura
Original Assignee
Halo Lsi Design & Device Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Halo Lsi Design & Device Tech filed Critical Halo Lsi Design & Device Tech
Application granted granted Critical
Publication of ATE373862T1 publication Critical patent/ATE373862T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
AT02368073T 2001-07-06 2002-07-05 Steuergate- und wortleitungs- spannungserhöhungsverfahren für zwilling-monos- zellenspeichern ATE373862T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US30373801P 2001-07-06 2001-07-06

Publications (1)

Publication Number Publication Date
ATE373862T1 true ATE373862T1 (de) 2007-10-15

Family

ID=23173471

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02368073T ATE373862T1 (de) 2001-07-06 2002-07-05 Steuergate- und wortleitungs- spannungserhöhungsverfahren für zwilling-monos- zellenspeichern

Country Status (7)

Country Link
US (1) US6735118B2 (de)
EP (1) EP1274096B1 (de)
JP (1) JP2003151290A (de)
KR (1) KR20030011261A (de)
AT (1) ATE373862T1 (de)
DE (1) DE60222504T2 (de)
TW (1) TWI220254B (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6897522B2 (en) * 2001-10-31 2005-05-24 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US6925007B2 (en) * 2001-10-31 2005-08-02 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US6795349B2 (en) * 2002-02-28 2004-09-21 Sandisk Corporation Method and system for efficiently reading and programming of dual cell memory elements
JP2004199738A (ja) * 2002-12-16 2004-07-15 Seiko Epson Corp 不揮発性記憶装置
US20050251617A1 (en) * 2004-05-07 2005-11-10 Sinclair Alan W Hybrid non-volatile memory system
CN100426420C (zh) * 2004-11-24 2008-10-15 上海华虹Nec电子有限公司 用于低压非挥发存储器的字线升压电路
US7295485B2 (en) * 2005-07-12 2007-11-13 Atmel Corporation Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations
US7936604B2 (en) * 2005-08-30 2011-05-03 Halo Lsi Inc. High speed operation method for twin MONOS metal bit array
US7388252B2 (en) * 2005-09-23 2008-06-17 Macronix International Co., Ltd. Two-bits per cell not-and-gate (NAND) nitride trap memory
US7369437B2 (en) 2005-12-16 2008-05-06 Sandisk Corporation System for reading non-volatile storage with efficient setup
US7545675B2 (en) 2005-12-16 2009-06-09 Sandisk Corporation Reading non-volatile storage with efficient setup
US7626865B2 (en) 2006-06-13 2009-12-01 Micron Technology, Inc. Charge pump operation in a non-volatile memory device
US7492633B2 (en) 2006-06-19 2009-02-17 Sandisk Corporation System for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines
US7349261B2 (en) 2006-06-19 2008-03-25 Sandisk Corporation Method for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines
JP2009076188A (ja) * 2007-08-24 2009-04-09 Renesas Technology Corp 不揮発性半導体記憶装置
JP2010020848A (ja) * 2008-07-11 2010-01-28 Nec Electronics Corp 不揮発性半導体メモリ及びデータ読み出し方法
JP5404149B2 (ja) * 2009-04-16 2014-01-29 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR101662703B1 (ko) * 2010-06-09 2016-10-14 삼성전자 주식회사 플래시 메모리 장치 및 플래시 메모리 장치의 독출 방법
KR102182583B1 (ko) 2016-05-17 2020-11-24 실리콘 스토리지 테크놀로지 인크 비휘발성 메모리 어레이를 사용하는 딥러닝 신경망 분류기
CN110610942B (zh) * 2018-06-15 2023-07-28 硅存储技术公司 用于减少闪存存储器系统中字线和控制栅极线之间的耦合的方法和装置
US11270763B2 (en) 2019-01-18 2022-03-08 Silicon Storage Technology, Inc. Neural network classifier using array of three-gate non-volatile memory cells
US11423979B2 (en) * 2019-04-29 2022-08-23 Silicon Storage Technology, Inc. Decoding system and physical layout for analog neural memory in deep learning artificial neural network

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
JP2000200842A (ja) * 1998-11-04 2000-07-18 Sony Corp 不揮発性半導体記憶装置、製造方法および書き込み方法
US6255166B1 (en) * 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array
US6248633B1 (en) * 1999-10-25 2001-06-19 Halo Lsi Design & Device Technology, Inc. Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory
JP3573691B2 (ja) * 2000-07-03 2004-10-06 シャープ株式会社 不揮発性半導体記憶装置およびその製造方法
DE60133259D1 (de) * 2000-12-15 2008-04-30 Halo Lsi Design & Device Tech Schnelles Programmier- und Programmierverifikationsverfahren
US6531350B2 (en) * 2001-02-22 2003-03-11 Halo, Inc. Twin MONOS cell fabrication method and array organization

Also Published As

Publication number Publication date
KR20030011261A (ko) 2003-02-07
US20030007387A1 (en) 2003-01-09
EP1274096B1 (de) 2007-09-19
DE60222504D1 (de) 2007-10-31
TWI220254B (en) 2004-08-11
EP1274096A3 (de) 2004-12-22
EP1274096A2 (de) 2003-01-08
US6735118B2 (en) 2004-05-11
JP2003151290A (ja) 2003-05-23
DE60222504T2 (de) 2008-06-19

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