ATE376691T1 - Verfahren und prozessor zur parallelen verarbeitung einer logikereignis-simulation - Google Patents
Verfahren und prozessor zur parallelen verarbeitung einer logikereignis-simulationInfo
- Publication number
- ATE376691T1 ATE376691T1 AT02700539T AT02700539T ATE376691T1 AT E376691 T1 ATE376691 T1 AT E376691T1 AT 02700539 T AT02700539 T AT 02700539T AT 02700539 T AT02700539 T AT 02700539T AT E376691 T1 ATE376691 T1 AT E376691T1
- Authority
- AT
- Austria
- Prior art keywords
- processor
- associative memory
- segments
- memory mechanism
- segment
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/IE2002/000023 WO2003079237A1 (en) | 2002-02-22 | 2002-02-22 | A method and a processor for parallel processing of logic event simulation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE376691T1 true ATE376691T1 (de) | 2007-11-15 |
Family
ID=27840067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT02700539T ATE376691T1 (de) | 2002-02-22 | 2002-02-22 | Verfahren und prozessor zur parallelen verarbeitung einer logikereignis-simulation |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US20050228629A1 (de) |
| EP (1) | EP1476828B1 (de) |
| AT (1) | ATE376691T1 (de) |
| AU (1) | AU2002233604A1 (de) |
| DE (1) | DE60223180D1 (de) |
| WO (1) | WO2003079237A1 (de) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7114026B1 (en) * | 2002-06-17 | 2006-09-26 | Sandeep Khanna | CAM device having multiple index generators |
| US20080092092A1 (en) * | 2004-10-04 | 2008-04-17 | Damian Jude Dalton | Method and Processor for Power Analysis in Digital Circuits |
| US8843885B2 (en) * | 2009-12-28 | 2014-09-23 | Mitsubishi Electric Corporation | Program creation support device |
| US8738350B2 (en) * | 2010-03-04 | 2014-05-27 | Synopsys, Inc. | Mixed concurrent and serial logic simulation of hardware designs |
| CN114841103B (zh) * | 2022-07-01 | 2022-09-27 | 南昌大学 | 门级电路的并行仿真方法、系统、存储介质及设备 |
| CN117112452B (zh) * | 2023-08-24 | 2024-04-02 | 上海合芯数字科技有限公司 | 寄存器模拟配置方法、装置、计算机设备和存储介质 |
| CN118210611B (zh) * | 2024-03-29 | 2024-10-01 | 重庆赛力斯凤凰智创科技有限公司 | 逻辑事件执行方法、装置、电子设备及存储介质 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0816470A (ja) * | 1994-07-04 | 1996-01-19 | Hitachi Ltd | 並列計算機 |
| WO2001001298A2 (en) * | 1999-06-28 | 2001-01-04 | University College Dublin | Logic event simulation |
| US20070219771A1 (en) * | 2005-12-01 | 2007-09-20 | Verheyen Henry T | Branching and Behavioral Partitioning for a VLIW Processor |
-
2002
- 2002-02-22 AT AT02700539T patent/ATE376691T1/de not_active IP Right Cessation
- 2002-02-22 EP EP02700539A patent/EP1476828B1/de not_active Expired - Lifetime
- 2002-02-22 DE DE60223180T patent/DE60223180D1/de not_active Expired - Lifetime
- 2002-02-22 AU AU2002233604A patent/AU2002233604A1/en not_active Abandoned
- 2002-02-22 WO PCT/IE2002/000023 patent/WO2003079237A1/en not_active Ceased
- 2002-02-22 US US10/505,260 patent/US20050228629A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| EP1476828B1 (de) | 2007-10-24 |
| AU2002233604A1 (en) | 2003-09-29 |
| EP1476828A1 (de) | 2004-11-17 |
| US20050228629A1 (en) | 2005-10-13 |
| DE60223180D1 (de) | 2007-12-06 |
| WO2003079237A1 (en) | 2003-09-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR950020755A (ko) | 일치 검출 회로를 갖고 있는 반도체 메모리 디바이스 및 테스트 방법 | |
| ATE514982T1 (de) | Verfahren und vorrichtungen zur auswertung regulärer ausdrücke beliebiger grösse | |
| ATE434228T1 (de) | Verfahren und vorrichtung für widerstand gegen hardware-hacking durch interne registerschnittstelle | |
| ATE346309T1 (de) | Verbindung mehrerer testzugriffsportsteuerungsvorrichtungen durch ein einzeltestzugriffsport | |
| Wei et al. | Self-consistency and consistency-based detection and diagnosis of malicious circuitry | |
| ATE376691T1 (de) | Verfahren und prozessor zur parallelen verarbeitung einer logikereignis-simulation | |
| US10957391B2 (en) | Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits | |
| Fan et al. | A gate-level method for transistor-level bridging fault diagnosis | |
| US6810507B2 (en) | Method and apparatus for isolating the root of indeterminate logic values in an HDL simulation | |
| JPH0275019A (ja) | 桁上げ選択加算器 | |
| Chaudhary et al. | Low-power high-performance NAND match line content addressable memories | |
| DE60024088D1 (de) | Ereignis-simulation einer schaltkreislogik | |
| CN104849648B (zh) | 一种提高木马活性的测试向量生成方法 | |
| KR930015431A (ko) | 중재자 | |
| Saab | Parallel-concurrent fault simulation | |
| US6877142B2 (en) | Timing verifier for MOS devices and related method | |
| US20190138679A1 (en) | Coding and synthesizing a state machine in state groups | |
| US6654937B1 (en) | Register file timing using static timing tools | |
| US6438732B1 (en) | Method and apparatus for modeling gate capacitance of symmetrically and asymmetrically sized differential cascode voltage swing logic (DCVSL) | |
| Chou et al. | Finding reset nondeterminism in RTL designs-scalable X-analysis methodology and case study | |
| Thatcher et al. | Automatic partitioning and dynamic mixed-mode simulation | |
| Fotovatikhah et al. | A new approach to model the effect of topology on testing using boundary scan | |
| CN115292102A (zh) | 仿真方法、电子设备、可读存储介质 | |
| JP4683873B2 (ja) | 論理回路および半導体集積回路 | |
| Saab et al. | Parallel-Concurrent Versus Concurrent Fault Simulation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |