ATE376719T1 - Verfahren zur dämpfung unerwünchten frequenzen während der abtastung eines nachrichtensignals - Google Patents

Verfahren zur dämpfung unerwünchten frequenzen während der abtastung eines nachrichtensignals

Info

Publication number
ATE376719T1
ATE376719T1 AT01000143T AT01000143T ATE376719T1 AT E376719 T1 ATE376719 T1 AT E376719T1 AT 01000143 T AT01000143 T AT 01000143T AT 01000143 T AT01000143 T AT 01000143T AT E376719 T1 ATE376719 T1 AT E376719T1
Authority
AT
Austria
Prior art keywords
signal
message signal
during sampling
frequencies during
unwanted frequencies
Prior art date
Application number
AT01000143T
Other languages
English (en)
Inventor
Baher S Haroun
Gabriel J Gomez
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of ATE376719T1 publication Critical patent/ATE376719T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0626—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by filtering
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/344—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Analogue/Digital Conversion (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Circuits Of Receivers In General (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
AT01000143T 2000-05-15 2001-05-15 Verfahren zur dämpfung unerwünchten frequenzen während der abtastung eines nachrichtensignals ATE376719T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US20490200P 2000-05-15 2000-05-15

Publications (1)

Publication Number Publication Date
ATE376719T1 true ATE376719T1 (de) 2007-11-15

Family

ID=22759956

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01000143T ATE376719T1 (de) 2000-05-15 2001-05-15 Verfahren zur dämpfung unerwünchten frequenzen während der abtastung eines nachrichtensignals

Country Status (6)

Country Link
US (1) US6621441B2 (de)
EP (1) EP1164707B1 (de)
JP (1) JP2002064380A (de)
CN (1) CN1263318C (de)
AT (1) ATE376719T1 (de)
DE (1) DE60131048T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6961746B1 (en) * 2001-06-12 2005-11-01 Analog Devices, Inc. Current integration circuit with course quantization and small integration capacitor
US6952594B2 (en) 2002-11-22 2005-10-04 Agilent Technologies, Inc. Dual-mode RF communication device
KR100828271B1 (ko) * 2005-08-05 2008-05-07 산요덴키가부시키가이샤 스위치 제어 회로, δ∑ 변조 회로, 및 δ∑ 변조형 ａｄ컨버터
JP4662826B2 (ja) * 2005-08-05 2011-03-30 三洋電機株式会社 スイッチ制御回路、δς変調回路、及びδς変調型ａｄコンバータ
JP5022672B2 (ja) * 2005-11-22 2012-09-12 パナソニック株式会社 サンプリングミキサおよび受信機
JP5046622B2 (ja) * 2005-12-13 2012-10-10 パナソニック株式会社 サンプリングフィルタ装置
WO2008050630A1 (en) * 2006-10-23 2008-05-02 Panasonic Corporation Sampling filter device and radio communication device
US8779956B2 (en) * 2006-12-01 2014-07-15 Intersil Americas Inc. Sigma-delta converter system and method
US7605732B2 (en) * 2007-01-29 2009-10-20 Texas Instruments Incorporated Systems and methods for kickback reduction in an ADC
US7904048B2 (en) * 2007-06-29 2011-03-08 Texas Instruments Incorporated Multi-tap direct sub-sampling mixing system for wireless receivers
US7489263B1 (en) 2007-09-28 2009-02-10 Cirrus Logic, Inc. Discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with multi-phase reference application
US7492296B1 (en) * 2007-09-28 2009-02-17 Cirrus Logic, Inc. Discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with input signal and common-mode current nulling
AU2008317311B2 (en) 2007-10-24 2013-07-04 Nuvasive, Inc. Surgical trajectory monitoring system and related methods
US8195221B2 (en) * 2008-06-30 2012-06-05 Intel Corporation Loop delay compensation for continuous time sigma delta analog to digital converter
WO2010020965A2 (en) * 2008-08-22 2010-02-25 Nxp B.V. Device and method for offset compensation based on hysteresis tracking
US8768997B2 (en) 2009-02-05 2014-07-01 Qualcomm Incorporated Passive switched-capacitor filters conforming to power constraint
EP2477418B1 (de) * 2011-01-12 2014-06-04 Nxp B.V. Signalverarbeitungsverfahren
US10224757B2 (en) 2016-12-28 2019-03-05 Texas Instruments Incorporated Methods and apparatus for antenna signal limiter for radio frequency identification transponder
US10038579B1 (en) * 2017-03-15 2018-07-31 Texas Instruments Incorporated Integrated circuits and transponder circuitry with shared modulation capacitor for 3D transponder uplink modulation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4939516B1 (en) * 1988-06-13 1993-10-26 Crystal Semiconductor Corporation Chopper stabilized delta-sigma analog-to-digital converter
US5079550A (en) * 1989-10-27 1992-01-07 Crystal Semiconductor Corporation Combining continuous time and discrete time signal processing in a delta-sigma modulator
US5477481A (en) * 1991-02-15 1995-12-19 Crystal Semiconductor Corporation Switched-capacitor integrator with chopper stabilization performed at the sampling rate
US6005506A (en) * 1997-12-09 1999-12-21 Qualcomm, Incorporated Receiver with sigma-delta analog-to-digital converter for sampling a received signal
US6285311B1 (en) * 1999-04-19 2001-09-04 National Semiconductor Corporation Switched capacitor filter circuit having reduced offsets and allowing for offset compensation without a closed feedback loop

Also Published As

Publication number Publication date
EP1164707B1 (de) 2007-10-24
EP1164707A2 (de) 2001-12-19
DE60131048D1 (de) 2007-12-06
JP2002064380A (ja) 2002-02-28
US6621441B2 (en) 2003-09-16
CN1263318C (zh) 2006-07-05
US20020030617A1 (en) 2002-03-14
DE60131048T2 (de) 2008-08-07
CN1324194A (zh) 2001-11-28
EP1164707A3 (de) 2004-12-01

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