ATE377793T1 - Verfaren und vorrichtung zum einteilen von anforderungen für einen dynamischen direktzugriffsspeicherbaustein - Google Patents

Verfaren und vorrichtung zum einteilen von anforderungen für einen dynamischen direktzugriffsspeicherbaustein

Info

Publication number
ATE377793T1
ATE377793T1 AT02713653T AT02713653T ATE377793T1 AT E377793 T1 ATE377793 T1 AT E377793T1 AT 02713653 T AT02713653 T AT 02713653T AT 02713653 T AT02713653 T AT 02713653T AT E377793 T1 ATE377793 T1 AT E377793T1
Authority
AT
Austria
Prior art keywords
memory device
random access
access memory
dynamic random
assessing
Prior art date
Application number
AT02713653T
Other languages
English (en)
Inventor
Wolf-Dietrich Weber
Original Assignee
Sonics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25525212&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=ATE377793(T1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Sonics Inc filed Critical Sonics Inc
Application granted granted Critical
Publication of ATE377793T1 publication Critical patent/ATE377793T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT02713653T 2001-10-12 2002-02-21 Verfaren und vorrichtung zum einteilen von anforderungen für einen dynamischen direktzugriffsspeicherbaustein ATE377793T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/977,510 US6961834B2 (en) 2001-10-12 2001-10-12 Method and apparatus for scheduling of requests to dynamic random access memory device

Publications (1)

Publication Number Publication Date
ATE377793T1 true ATE377793T1 (de) 2007-11-15

Family

ID=25525212

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02713653T ATE377793T1 (de) 2001-10-12 2002-02-21 Verfaren und vorrichtung zum einteilen von anforderungen für einen dynamischen direktzugriffsspeicherbaustein

Country Status (6)

Country Link
US (1) US6961834B2 (de)
EP (1) EP1435039B1 (de)
JP (1) JP4095032B2 (de)
AT (1) ATE377793T1 (de)
DE (1) DE60223394T2 (de)
WO (1) WO2003040927A1 (de)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6804738B2 (en) * 2001-10-12 2004-10-12 Sonics, Inc. Method and apparatus for scheduling a resource to meet quality-of-service restrictions
US7194561B2 (en) * 2001-10-12 2007-03-20 Sonics, Inc. Method and apparatus for scheduling requests to a resource using a configurable threshold
US7194566B2 (en) * 2002-05-03 2007-03-20 Sonics, Inc. Communication system and method with configurable posting points
US7356633B2 (en) * 2002-05-03 2008-04-08 Sonics, Inc. Composing on-chip interconnects with configurable interfaces
US7254603B2 (en) * 2002-05-03 2007-08-07 Sonics, Inc. On-chip inter-network performance optimization using configurable performance parameters
US7302691B2 (en) * 2002-05-10 2007-11-27 Sonics, Incorporated Scalable low bandwidth multicast handling in mixed core systems
US7836252B2 (en) 2002-08-29 2010-11-16 Micron Technology, Inc. System and method for optimizing interconnections of memory devices in a multichip module
US7603441B2 (en) * 2002-12-27 2009-10-13 Sonics, Inc. Method and apparatus for automatic configuration of multiple on-chip interconnects
US7827283B2 (en) * 2003-02-19 2010-11-02 International Business Machines Corporation System for managing and controlling storage access requirements
US7245145B2 (en) 2003-06-11 2007-07-17 Micron Technology, Inc. Memory module and method having improved signal routing topology
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7665069B2 (en) * 2003-10-31 2010-02-16 Sonics, Inc. Method and apparatus for establishing a quality of service model
US9087036B1 (en) 2004-08-12 2015-07-21 Sonics, Inc. Methods and apparatuses for time annotated transaction level modeling
US8504992B2 (en) * 2003-10-31 2013-08-06 Sonics, Inc. Method and apparatus for establishing a quality of service model
US7181584B2 (en) 2004-02-05 2007-02-20 Micron Technology, Inc. Dynamic command and/or address mirroring system and method for memory modules
US7366864B2 (en) * 2004-03-08 2008-04-29 Micron Technology, Inc. Memory hub architecture having programmable lane widths
US7120723B2 (en) 2004-03-25 2006-10-10 Micron Technology, Inc. System and method for memory hub-based expansion bus
US7590797B2 (en) 2004-04-08 2009-09-15 Micron Technology, Inc. System and method for optimizing interconnections of components in a multichip memory module
US7392331B2 (en) 2004-08-31 2008-06-24 Micron Technology, Inc. System and method for transmitting data packets in a computer system having a memory hub architecture
US7681196B2 (en) * 2004-11-18 2010-03-16 Oracle International Corporation Providing optimal number of threads to applications performing multi-tasking using threads
US20060112240A1 (en) * 2004-11-24 2006-05-25 Walker Robert M Priority scheme for executing commands in memories
EP1880296A1 (de) * 2005-05-04 2008-01-23 Nxp B.V. Speichersteuerung und verfahren zur steuerung des zugangs zu einem speicher sowie system mit einer speichersteuerung
KR100784385B1 (ko) * 2005-08-10 2007-12-11 삼성전자주식회사 공유 자원에 대한 접근 요청을 중재하는 시스템 및 방법
CN101331464A (zh) * 2005-12-16 2008-12-24 日本电气株式会社 存储区域分配系统及方法和控制装置
US8868397B2 (en) * 2006-11-20 2014-10-21 Sonics, Inc. Transaction co-validation across abstraction layers
US7814243B2 (en) * 2007-06-01 2010-10-12 Sonics, Inc. Shared storage for multi-threaded ordered queues in an interconnect
US9588810B2 (en) * 2007-08-08 2017-03-07 Microsoft Technology Licensing, Llc Parallelism-aware memory request scheduling in shared memory controllers
US8260990B2 (en) * 2007-11-19 2012-09-04 Qualcomm Incorporated Selective preclusion of a bus access request
US8180975B2 (en) * 2008-02-26 2012-05-15 Microsoft Corporation Controlling interference in shared memory systems using parallelism-aware batch scheduling
US8607234B2 (en) 2009-07-22 2013-12-10 Empire Technology Development, Llc Batch scheduling with thread segregation and per thread type marking caps
US8799912B2 (en) * 2009-07-22 2014-08-05 Empire Technology Development Llc Application selection of memory request scheduling
US8839255B2 (en) * 2009-07-23 2014-09-16 Empire Technology Development Llc Scheduling of threads by batch scheduling
US8972995B2 (en) 2010-08-06 2015-03-03 Sonics, Inc. Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads
US8438306B2 (en) 2010-11-02 2013-05-07 Sonics, Inc. Apparatus and methods for on layer concurrency in an integrated circuit
KR101292309B1 (ko) * 2011-12-27 2013-07-31 숭실대학교산학협력단 반도체칩 및 메모리 제어방법, 그리고 그 방법을 컴퓨터에서 실행시키기 위한 프로그램을 기록한 기록매체
US9563369B2 (en) * 2014-04-14 2017-02-07 Microsoft Technology Licensing, Llc Fine-grained bandwidth provisioning in a memory controller
KR20170136382A (ko) * 2016-06-01 2017-12-11 주식회사 맴레이 메모리 컨트롤러, 그리고 이를 포함하는 메모리 모듈 및 프로세서
US10572399B2 (en) * 2016-07-13 2020-02-25 Qualcomm Incorporated Memory request arbitration
US10481944B2 (en) * 2017-08-09 2019-11-19 Xilinx, Inc. Adaptive quality of service control circuit
DE102024204811A1 (de) 2024-05-24 2025-11-27 Infineon Technologies Ag Halbleitervorrichtung mit arbitration

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5274769A (en) 1988-08-29 1993-12-28 Fujitsu Limited System for transferring data between blocks
US5287464A (en) 1990-10-24 1994-02-15 Zilog, Inc. Semiconductor multi-device system with logic means for controlling the operational mode of a set of input/output data bus drivers
JP2575557B2 (ja) 1990-11-13 1997-01-29 インターナショナル・ビジネス・マシーンズ・コーポレイション スーパーコンピユータシステム
US5218456A (en) 1991-07-22 1993-06-08 Xerox Corporation Disk bandwidth allocations to prioritize disk requests
US5530901A (en) 1991-11-28 1996-06-25 Ricoh Company, Ltd. Data Transmission processing system having DMA channels running cyclically to execute data transmission from host to memory and from memory to processing unit successively
JP2531903B2 (ja) 1992-06-22 1996-09-04 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュ―タ・システムおよびシステム拡張装置
US5664153A (en) 1993-04-21 1997-09-02 Intel Corporation Page open/close scheme based on high order address bit and likelihood of page access
US5469473A (en) 1994-04-15 1995-11-21 Texas Instruments Incorporated Transceiver circuit with transition detection
SE515901C2 (sv) 1995-12-28 2001-10-22 Dynarc Ab Resursadministrering, plan och arrangemang
US5809538A (en) 1996-02-07 1998-09-15 General Instrument Corporation DRAM arbiter for video decoder
US5912872A (en) 1996-09-27 1999-06-15 Digital Optics Corporation Integrated optical apparatus providing separated beams on a detector and associated methods
US5926649A (en) 1996-10-23 1999-07-20 Industrial Technology Research Institute Media server for storage and retrieval of voluminous multimedia data
US5996037A (en) 1997-06-03 1999-11-30 Lsi Logic Corporation System and method for arbitrating multi-function access to a system bus
GB2326065B (en) 1997-06-05 2002-05-29 Mentor Graphics Corp A scalable processor independent on-chip bus
US6092137A (en) 1997-11-26 2000-07-18 Industrial Technology Research Institute Fair data bus arbitration system which assigns adjustable priority values to competing sources
US6023720A (en) * 1998-02-09 2000-02-08 Matsushita Electric Industrial Co., Ltd. Simultaneous processing of read and write requests using optimized storage partitions for read and write request deadlines
US6335932B2 (en) 1998-07-08 2002-01-01 Broadcom Corporation High performance self balancing low cost network switching architecture based on distributed hierarchical shared memory
US6363445B1 (en) 1998-10-15 2002-03-26 Micron Technology, Inc. Method of bus arbitration using requesting device bandwidth and priority ranking
US6167445A (en) 1998-10-26 2000-12-26 Cisco Technology, Inc. Method and apparatus for defining and implementing high-level quality of service policies in computer networks
US6195724B1 (en) * 1998-11-16 2001-02-27 Infineon Technologies Ag Methods and apparatus for prioritization of access to external devices
US6253269B1 (en) 1998-12-22 2001-06-26 3Com Corporation Bus arbiter system and method for managing communication buses
CN1452745A (zh) * 2000-04-03 2003-10-29 先进微装置公司 包含具有改良存储器请求仲裁机制的存储器控制器的总线桥
US6330225B1 (en) 2000-05-26 2001-12-11 Sonics, Inc. Communication system and method for different quality of service guarantees for different data flows

Also Published As

Publication number Publication date
EP1435039B1 (de) 2007-11-07
EP1435039A1 (de) 2004-07-07
US6961834B2 (en) 2005-11-01
US20030074519A1 (en) 2003-04-17
JP2005508550A (ja) 2005-03-31
EP1435039A4 (de) 2006-06-28
WO2003040927A1 (en) 2003-05-15
DE60223394T2 (de) 2008-08-28
JP4095032B2 (ja) 2008-06-04
DE60223394D1 (de) 2007-12-20

Similar Documents

Publication Publication Date Title
ATE377793T1 (de) Verfaren und vorrichtung zum einteilen von anforderungen für einen dynamischen direktzugriffsspeicherbaustein
EP1435044A4 (de) Verfahren und vorrichtung zur einplanung von anforderungen unter verwendung geordneter stufen von einplanungskriterien
TW200729462A (en) Phase-change random access memory device and method of operating the same
WO2004041069A3 (en) Methods and devices for determining brain state
DE69831857D1 (de) Verfahren und Vorrichtung zum Zeitplanen von Prozessen für Betriebsmittelzuteilung
DE60221530D1 (de) Verfahren und vorrichtung zum unterdrücken von tönen, die durch dem-algorithmen (cyclic dynamic element matching) verursacht werden
DE60228470D1 (de) Verfahren, vorrichtung und system für einen mobil-web-client
ATE435456T1 (de) Verschiedene verfahren und vorrichtungen zur arbitrierung zwischen funktionalitätsblöcken
MY136470A (en) Memory adapted to provide dedicated and or shared memory to multiple processors and method therefor
DE60207869D1 (de) Verfahren und system zum verarbeiten von informationen in einem elektronischen gerät
TW200715216A (en) Apparatus and methods for graphics processing
DE50115219D1 (de) Verfahren und vorrichtung zur überwachung einer datenverarbeitung und -übertragung
DE602005026892D1 (de) Chipkarte für mehrere Anwendungen
ATE367014T1 (de) Verfahren und anordnung zum zuweisen von namen zu einrichtungen in einem netzwerk
ATE408882T1 (de) Verfahren und vorrichtung zum teilweisen auffrischen von drams
EP2650828A3 (de) UICC-Vorrichtung und zugehörige Verfahren
EP4521257A4 (de) Statistisches verfahren für speicherzugriffspopularität, zugehörige vorrichtung und vorrichtung
DE60103451D1 (de) Verfahren und Vorrichtung für das Simulieren von Lasten an Hebezeugen
EP4133797C0 (de) Verfahren zur bereitstellung von zugang für vorrichtungen mit reduzierter kapazität, und benutzergerät dafür
DE60232748D1 (de) Verfahren und vorrichtung zur planung einer halbduplexübertragung
DE60332654D1 (de) Speicherverwaltungsverfahren und einrichtung
DE60239012D1 (de) Verfahren zum identifizieren von mustern in biologischen systemen und deren anwendungen
EP4280744A4 (de) Ressourcenzuweisungsverfahren, ressourcenauswahlverfahren, vorrichtung und speichermedium
DE60225612D1 (de) Verfahren und Vorrichtung zum Erfrischen von Referenzzellen
DE50110167D1 (de) Ladenwaage zum abwickeln einzelner vorgänge

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties