ATE379878T1 - Schaltung für synchrone mirror-verzögerung (smd) und verfahren mit einem zähler und bidirektionale verzögerungsleitung mit verringerter grösse - Google Patents

Schaltung für synchrone mirror-verzögerung (smd) und verfahren mit einem zähler und bidirektionale verzögerungsleitung mit verringerter grösse

Info

Publication number
ATE379878T1
ATE379878T1 AT03739222T AT03739222T ATE379878T1 AT E379878 T1 ATE379878 T1 AT E379878T1 AT 03739222 T AT03739222 T AT 03739222T AT 03739222 T AT03739222 T AT 03739222T AT E379878 T1 ATE379878 T1 AT E379878T1
Authority
AT
Austria
Prior art keywords
delay
delay line
smd
clock signal
input clock
Prior art date
Application number
AT03739222T
Other languages
English (en)
Inventor
Howard Kirsch
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE379878T1 publication Critical patent/ATE379878T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Pulse Circuits (AREA)
  • Dram (AREA)
AT03739222T 2002-06-20 2003-06-19 Schaltung für synchrone mirror-verzögerung (smd) und verfahren mit einem zähler und bidirektionale verzögerungsleitung mit verringerter grösse ATE379878T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/176,865 US6621316B1 (en) 2002-06-20 2002-06-20 Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line

Publications (1)

Publication Number Publication Date
ATE379878T1 true ATE379878T1 (de) 2007-12-15

Family

ID=27804701

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03739222T ATE379878T1 (de) 2002-06-20 2003-06-19 Schaltung für synchrone mirror-verzögerung (smd) und verfahren mit einem zähler und bidirektionale verzögerungsleitung mit verringerter grösse

Country Status (9)

Country Link
US (2) US6621316B1 (de)
EP (1) EP1532737B1 (de)
KR (1) KR100847429B1 (de)
CN (1) CN100542036C (de)
AT (1) ATE379878T1 (de)
AU (1) AU2003245594A1 (de)
DE (1) DE60317796T2 (de)
TW (1) TWI324446B (de)
WO (1) WO2004001972A1 (de)

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US9356769B2 (en) * 2014-09-24 2016-05-31 Qualcomm Incorporated Synchronous reset and phase detecting for interchain local oscillator (LO) divider phase alignment
US20170207777A1 (en) * 2016-01-15 2017-07-20 Macronix International Co., Ltd. Integrated circuit device and delay circuit device having varied delay time structure
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US10148269B1 (en) 2017-07-24 2018-12-04 Micron Technology, Inc. Dynamic termination edge control
US10153014B1 (en) 2017-08-17 2018-12-11 Micron Technology, Inc. DQS-offset and read-RTT-disable edge control
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Also Published As

Publication number Publication date
DE60317796T2 (de) 2008-10-30
AU2003245594A1 (en) 2004-01-06
US6621316B1 (en) 2003-09-16
TWI324446B (en) 2010-05-01
US20030234673A1 (en) 2003-12-25
CN100542036C (zh) 2009-09-16
EP1532737A1 (de) 2005-05-25
KR20050024413A (ko) 2005-03-10
EP1532737B1 (de) 2007-11-28
TW200418268A (en) 2004-09-16
CN1675838A (zh) 2005-09-28
DE60317796D1 (de) 2008-01-10
KR100847429B1 (ko) 2008-07-21
EP1532737A4 (de) 2005-11-16
US6924686B2 (en) 2005-08-02
WO2004001972A1 (en) 2003-12-31

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Legal Events

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