ATE381101T1 - Differenz-dual-floating-gate-schaltung und programmierverfahren - Google Patents

Differenz-dual-floating-gate-schaltung und programmierverfahren

Info

Publication number
ATE381101T1
ATE381101T1 AT04700610T AT04700610T ATE381101T1 AT E381101 T1 ATE381101 T1 AT E381101T1 AT 04700610 T AT04700610 T AT 04700610T AT 04700610 T AT04700610 T AT 04700610T AT E381101 T1 ATE381101 T1 AT E381101T1
Authority
AT
Austria
Prior art keywords
floating gate
gate circuit
dual floating
programming method
during
Prior art date
Application number
AT04700610T
Other languages
English (en)
Inventor
William Owen
Original Assignee
Xicor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xicor Inc filed Critical Xicor Inc
Application granted granted Critical
Publication of ATE381101T1 publication Critical patent/ATE381101T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS

Landscapes

  • Non-Volatile Memory (AREA)
  • Logic Circuits (AREA)
  • Control Of Electrical Variables (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Read Only Memory (AREA)
  • Manipulation Of Pulses (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Electronic Switches (AREA)
AT04700610T 2003-01-07 2004-01-07 Differenz-dual-floating-gate-schaltung und programmierverfahren ATE381101T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/338,189 US6898123B2 (en) 2003-01-07 2003-01-07 Differential dual floating gate circuit and method for programming

Publications (1)

Publication Number Publication Date
ATE381101T1 true ATE381101T1 (de) 2007-12-15

Family

ID=32710966

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04700610T ATE381101T1 (de) 2003-01-07 2004-01-07 Differenz-dual-floating-gate-schaltung und programmierverfahren

Country Status (7)

Country Link
US (1) US6898123B2 (de)
EP (1) EP1588377B1 (de)
JP (1) JP4865537B2 (de)
CN (1) CN1754228B (de)
AT (1) ATE381101T1 (de)
DE (1) DE602004010617D1 (de)
WO (1) WO2004064115A2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7212446B2 (en) * 2002-09-16 2007-05-01 Impinj, Inc. Counteracting overtunneling in nonvolatile memory cells using charge extraction control
US7149118B2 (en) * 2002-09-16 2006-12-12 Impinj, Inc. Method and apparatus for programming single-poly pFET-based nonvolatile memory cells
US7113017B2 (en) * 2004-07-01 2006-09-26 Intersil Americas Inc. Floating gate analog voltage level shift circuit and method for producing a voltage reference that operates on a low supply voltage
US6870764B2 (en) * 2003-01-21 2005-03-22 Xicor Corporation Floating gate analog voltage feedback circuit
US7283390B2 (en) * 2004-04-21 2007-10-16 Impinj, Inc. Hybrid non-volatile memory
US8111558B2 (en) 2004-05-05 2012-02-07 Synopsys, Inc. pFET nonvolatile memory
CN101061449B (zh) * 2004-11-18 2010-08-11 Nxp股份有限公司 参考电压电路
CN1991396B (zh) * 2005-12-30 2010-05-05 鸿富锦精密工业（深圳）有限公司 电压检测装置
US8122307B1 (en) 2006-08-15 2012-02-21 Synopsys, Inc. One time programmable memory test structures and methods
US7616501B2 (en) * 2006-12-04 2009-11-10 Semiconductor Components Industries, L.L.C. Method for reducing charge loss in analog floating gate cell
US7894261B1 (en) 2008-05-22 2011-02-22 Synopsys, Inc. PFET nonvolatile memory
US7773424B2 (en) * 2008-05-23 2010-08-10 Freescale Semiconductor, Inc. Circuit for and an electronic device including a nonvolatile memory cell and a process of forming the electronic device
US7859911B2 (en) * 2008-07-21 2010-12-28 Triune Ip Llc Circuit and system for programming a floating gate
US7944744B2 (en) * 2009-06-30 2011-05-17 Sandisk Il Ltd. Estimating values related to discharge of charge-storing memory cells
US10782420B2 (en) 2017-12-18 2020-09-22 Thermo Eberline Llc Range-extended dosimeter
KR102331471B1 (ko) * 2019-08-23 2021-11-26 (주)아트로닉스 고전력 반도체 소자 및 그의 제조 방법

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4935702A (en) 1988-12-09 1990-06-19 Synaptics, Inc. Subthreshold CMOS amplifier with offset adaptation
US5059920A (en) 1988-12-09 1991-10-22 Synaptics, Incorporated CMOS amplifier with offset adaptation
US4980859A (en) 1989-04-07 1990-12-25 Xicor, Inc. NOVRAM cell using two differential decouplable nonvolatile memory elements
US4953928A (en) 1989-06-09 1990-09-04 Synaptics Inc. MOS device for long-term learning
US5095284A (en) 1990-09-10 1992-03-10 Synaptics, Incorporated Subthreshold CMOS amplifier with wide input voltage range
US5166562A (en) 1991-05-09 1992-11-24 Synaptics, Incorporated Writable analog reference voltage storage device
US5430670A (en) * 1993-11-08 1995-07-04 Elantec, Inc. Differential analog memory cell and method for adjusting same
JP2705605B2 (ja) * 1995-01-20 1998-01-28 日本電気株式会社 センスアンプ回路
US5875126A (en) 1995-09-29 1999-02-23 California Institute Of Technology Autozeroing floating gate amplifier
US5748534A (en) * 1996-03-26 1998-05-05 Invox Technology Feedback loop for reading threshold voltage
ITMI981193A1 (it) * 1998-05-29 1999-11-29 St Microelectronics Srl Dispositivo circuitale e relativo metodo per la propgrammazione di una cella di memoria non volatile a singola tensione di
US6297689B1 (en) 1999-02-03 2001-10-02 National Semiconductor Corporation Low temperature coefficient low power programmable CMOS voltage reference
EP1058270B1 (de) * 1999-06-04 2007-03-21 STMicroelectronics S.r.l. Vorspannungsstufe zum Vorspannen des Drains einer nichtflüchtigen Speicherzelle während des Auslesens
JP3933817B2 (ja) * 1999-06-24 2007-06-20 富士通株式会社 不揮発性メモリ回路

Also Published As

Publication number Publication date
US6898123B2 (en) 2005-05-24
WO2004064115A2 (en) 2004-07-29
CN1754228A (zh) 2006-03-29
EP1588377A2 (de) 2005-10-26
EP1588377A4 (de) 2006-04-05
JP2006520943A (ja) 2006-09-14
DE602004010617D1 (de) 2008-01-24
WO2004064115A9 (en) 2004-09-02
US20040135619A1 (en) 2004-07-15
JP4865537B2 (ja) 2012-02-01
CN1754228B (zh) 2010-05-05
WO2004064115A3 (en) 2005-02-24
EP1588377B1 (de) 2007-12-12

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