ATE392659T1 - Verfahren und diesbezügliche einrichtung zur hardwareorientierten umsetzung zwischen arithmetik- und boolscher zufallsmaskierung - Google Patents

Verfahren und diesbezügliche einrichtung zur hardwareorientierten umsetzung zwischen arithmetik- und boolscher zufallsmaskierung

Info

Publication number
ATE392659T1
ATE392659T1 AT04804633T AT04804633T ATE392659T1 AT E392659 T1 ATE392659 T1 AT E392659T1 AT 04804633 T AT04804633 T AT 04804633T AT 04804633 T AT04804633 T AT 04804633T AT E392659 T1 ATE392659 T1 AT E392659T1
Authority
AT
Austria
Prior art keywords
boolan
arithmetic
hardware
related device
oriented implementation
Prior art date
Application number
AT04804633T
Other languages
English (en)
Inventor
Jovan Golic
Original Assignee
Telecom Italia Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telecom Italia Spa filed Critical Telecom Italia Spa
Application granted granted Critical
Publication of ATE392659T1 publication Critical patent/ATE392659T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/764—Masking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • G06F2207/7223—Randomisation as countermeasure against side channel attacks
    • G06F2207/7233—Masking, e.g. (A**e)+r mod n
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/04—Masking or blinding
    • H04L2209/046—Masking or blinding of operations, operands or results of the operations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/08—Randomization, e.g. dummy operations or using noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Storage Device Security (AREA)
  • Hardware Redundancy (AREA)
  • Logic Circuits (AREA)
AT04804633T 2004-12-01 2004-12-01 Verfahren und diesbezügliche einrichtung zur hardwareorientierten umsetzung zwischen arithmetik- und boolscher zufallsmaskierung ATE392659T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2004/053203 WO2006058561A1 (en) 2004-12-01 2004-12-01 Method and related device for hardware-oriented conversion between arithmetic and boolean random masking

Publications (1)

Publication Number Publication Date
ATE392659T1 true ATE392659T1 (de) 2008-05-15

Family

ID=34979658

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04804633T ATE392659T1 (de) 2004-12-01 2004-12-01 Verfahren und diesbezügliche einrichtung zur hardwareorientierten umsetzung zwischen arithmetik- und boolscher zufallsmaskierung

Country Status (5)

Country Link
US (1) US8050402B2 (de)
EP (1) EP1836554B1 (de)
AT (1) ATE392659T1 (de)
DE (1) DE602004013206T2 (de)
WO (1) WO2006058561A1 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2443356B (en) * 2005-01-27 2008-08-06 Samsung Electronics Co Ltd Cryptographic logic circuits and method of performing logic operations
GB2443355B (en) * 2005-01-27 2008-08-06 Samsung Electronics Co Ltd Cryptographic logic circuits and method of performing logic operations
GB2443357B (en) * 2005-01-27 2008-10-08 Samsung Electronics Co Ltd Cryptographic logic circuits and method of performing logic operations
KR100725169B1 (ko) * 2005-01-27 2007-06-04 삼성전자주식회사 전력 분석 공격에 안전한 논리 연산 장치 및 방법
GB2443358A (en) * 2005-01-27 2008-04-30 Samsung Electronics Co Ltd Cryptographic logic circuits and method of performing logic operations
GB2443359B (en) * 2005-01-27 2008-10-01 Samsung Electronics Co Ltd Cryptographic logic circuits and method of performing logic operations
CN101147182B (zh) * 2005-03-31 2010-09-01 松下电器产业株式会社 数据加密装置及数据加密方法
WO2008064704A1 (en) * 2006-11-30 2008-06-05 Telecom Italia S.P.A Method and device for preventing information leakage attacks on a device implementing a cryptographic function
US8091139B2 (en) * 2007-11-01 2012-01-03 Discretix Technologies Ltd. System and method for masking arbitrary Boolean functions
DE102010028375A1 (de) * 2010-04-29 2011-11-03 Robert Bosch Gmbh Schutz vor kryptoanalytischen Seitenkanalattacken
FR2998692B1 (fr) * 2012-11-28 2015-01-30 Oberthur Technologies Procede de traitement cryptographique comprenant des operations booleennes sur des donnees masquees de maniere arithmetique, dispositifs et produit programme d'ordinateur correspondants
US9569616B2 (en) * 2013-12-12 2017-02-14 Cryptography Research, Inc. Gate-level masking
WO2015091583A1 (en) * 2013-12-20 2015-06-25 Koninklijke Philips N.V. Operator lifting in cryptographic algorithm
US9531384B1 (en) * 2014-12-01 2016-12-27 University Of South Florida Adiabatic dynamic differential logic for differential power analysis resistant secure integrated circuits
US9923719B2 (en) 2014-12-09 2018-03-20 Cryptography Research, Inc. Location aware cryptography
DE102015116049B3 (de) * 2015-09-23 2017-02-16 Infineon Technologies Ag Nulldetektionsschaltkreis und maskierter boolescher oder-schaltkreis
US10333699B1 (en) 2015-09-30 2019-06-25 Cryptography Research, Inc. Generating a pseudorandom number based on a portion of shares used in a cryptographic operation
US20180089426A1 (en) * 2016-09-29 2018-03-29 Government Of The United States As Represented By The Secretary Of The Air Force System, method, and apparatus for resisting hardware trojan induced leakage in combinational logics
US10389519B2 (en) * 2016-09-30 2019-08-20 International Business Machines Corporation Hardware based cryptographic side-channel attack prevention
DE102017002153A1 (de) * 2017-03-06 2018-09-06 Giesecke+Devrient Mobile Security Gmbh Übergang von einer booleschen Maskierung zu einer arithmetischen Maskierung
EP3557813A1 (de) * 2018-04-17 2019-10-23 Gemalto Sa Verfahren, das gegen seitenkanalangriffe gesichert ist, die eine arithmetische operation eines kryptografischen algorithmus durchführen, der boolesche und arithmetische operationen mischt.
EP3874364A4 (de) 2018-10-29 2022-08-03 Cryptography Research, Inc. Zeitkonstante sichere umwandlung von arithmetik in boolesche maske
US11507699B2 (en) * 2019-09-27 2022-11-22 Intel Corporation Processor with private pipeline
FR3101983B1 (fr) 2019-10-11 2021-11-12 St Microelectronics Grenoble 2 Détermination d'un bit indicateur
FR3101980B1 (fr) * 2019-10-11 2021-12-10 St Microelectronics Grenoble 2 Processeur
FR3101982B1 (fr) 2019-10-11 2024-03-08 St Microelectronics Grenoble 2 Détermination d'un bit indicateur
CN113922943B (zh) * 2021-09-29 2023-09-19 哲库科技(北京)有限公司 Sbox电路、运算方法及电子设备
FR3141261A1 (fr) * 2022-10-25 2024-04-26 Stmicroelectronics (Rousset) Sas Protection de données masquées
US12499277B2 (en) * 2023-04-10 2025-12-16 Nxp B.V. Flexible hardware accelerators for masking conversions with a power of two modulus
GB202405324D0 (en) * 2024-04-15 2024-05-29 Pqshield Ltd Efficient boolean-to-arithmetic mask conversion in hardware

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL139935A (en) * 1998-06-03 2005-06-19 Cryptography Res Inc Des and other cryptographic processes with leak minimization for smartcards and other cryptosystems
EP1088295B1 (de) * 1998-06-03 2007-08-15 Cryptography Research Inc. Ausgewogene kryptographische rechenmethode und apparat zur schlupfminimierung in smartcards und anderen kryptosystemen
US6295606B1 (en) * 1999-07-26 2001-09-25 Motorola, Inc. Method and apparatus for preventing information leakage attacks on a microelectronic assembly
GB2365153A (en) * 2000-01-28 2002-02-13 Simon William Moore Microprocessor resistant to power analysis with an alarm state
DE10201449C1 (de) 2002-01-16 2003-08-14 Infineon Technologies Ag Rechenwerk, Verfahren zum Ausführen einer Operation mit einem verschlüsselten Operanden, Carry-Select-Addierer und Kryptographieprozessor
DE10341096A1 (de) * 2003-09-05 2005-03-31 Giesecke & Devrient Gmbh Übergang zwischen maskierten Repräsentationen eines Wertes bei kryptographischen Berechnungen

Also Published As

Publication number Publication date
US20090112896A1 (en) 2009-04-30
DE602004013206D1 (de) 2008-05-29
US8050402B2 (en) 2011-11-01
EP1836554A1 (de) 2007-09-26
WO2006058561A1 (en) 2006-06-08
EP1836554B1 (de) 2008-04-16
DE602004013206T2 (de) 2009-05-14

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