FR3101983B1 - Détermination d'un bit indicateur - Google Patents

Détermination d'un bit indicateur Download PDF

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Publication number
FR3101983B1
FR3101983B1 FR1911347A FR1911347A FR3101983B1 FR 3101983 B1 FR3101983 B1 FR 3101983B1 FR 1911347 A FR1911347 A FR 1911347A FR 1911347 A FR1911347 A FR 1911347A FR 3101983 B1 FR3101983 B1 FR 3101983B1
Authority
FR
France
Prior art keywords
determining
indicator bit
processing
data item
binary data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1911347A
Other languages
English (en)
Other versions
FR3101983A1 (fr
Inventor
Rene Peyrard
Fabrice Romain
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
STMicroelectronics Grenoble 2 SAS
Original Assignee
STMicroelectronics Rousset SAS
STMicroelectronics Grenoble 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS, STMicroelectronics Grenoble 2 SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1911347A priority Critical patent/FR3101983B1/fr
Priority to US17/039,108 priority patent/US11714604B2/en
Priority to CN202011080609.6A priority patent/CN112653448B/zh
Publication of FR3101983A1 publication Critical patent/FR3101983A1/fr
Application granted granted Critical
Publication of FR3101983B1 publication Critical patent/FR3101983B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/40—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using contact-making devices, e.g. electromagnetic relay
    • G06F7/405—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using contact-making devices, e.g. electromagnetic relay binary
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Electromagnetism (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Storage Device Security (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Détermination d'un bit indicateur La présente description concerne un procédé de détermination d'un bit indicateur de retenue (Flag_C) d'une première donnée binaire (D) comportant une étape de traitement de ladite donnée binaire (D) masquée (D_M) par une opération de masquage, et ne comportant aucune étape de traitement de ladite première donnée (D). Figure pour l'abrégé : Fig. 3
FR1911347A 2019-10-11 2019-10-11 Détermination d'un bit indicateur Active FR3101983B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1911347A FR3101983B1 (fr) 2019-10-11 2019-10-11 Détermination d'un bit indicateur
US17/039,108 US11714604B2 (en) 2019-10-11 2020-09-30 Device and method for binary flag determination
CN202011080609.6A CN112653448B (zh) 2019-10-11 2020-10-10 用于二进制标志确定的设备和方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1911347 2019-10-11
FR1911347A FR3101983B1 (fr) 2019-10-11 2019-10-11 Détermination d'un bit indicateur

Publications (2)

Publication Number Publication Date
FR3101983A1 FR3101983A1 (fr) 2021-04-16
FR3101983B1 true FR3101983B1 (fr) 2021-11-12

Family

ID=69743318

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1911347A Active FR3101983B1 (fr) 2019-10-11 2019-10-11 Détermination d'un bit indicateur

Country Status (3)

Country Link
US (1) US11714604B2 (fr)
CN (1) CN112653448B (fr)
FR (1) FR3101983B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3101980B1 (fr) 2019-10-11 2021-12-10 St Microelectronics Grenoble 2 Processeur
FR3101982B1 (fr) 2019-10-11 2024-03-08 St Microelectronics Grenoble 2 Détermination d'un bit indicateur
TWI785954B (zh) * 2021-12-30 2022-12-01 新唐科技股份有限公司 節省進位加法器、安全加法器以及執行安全節省進位加法的方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2820914A1 (fr) * 2001-02-15 2002-08-16 Bull Cp8 Procede de securisation d'un ensemble electronique mettant en oeuvre en algorithme cryptographique utilisant des operations booleennes et des operations arithmetiques, et systeme embarque correspondant
US20040254966A1 (en) 2003-05-16 2004-12-16 Daewoo Educational Foundation Bit manipulation operation circuit and method in programmable processor
US7370180B2 (en) 2004-03-08 2008-05-06 Arm Limited Bit field extraction with sign or zero extend
ATE392659T1 (de) 2004-12-01 2008-05-15 Telecom Italia Spa Verfahren und diesbezügliche einrichtung zur hardwareorientierten umsetzung zwischen arithmetik- und boolscher zufallsmaskierung
KR100725169B1 (ko) * 2005-01-27 2007-06-04 삼성전자주식회사 전력 분석 공격에 안전한 논리 연산 장치 및 방법
JP4783104B2 (ja) 2005-09-29 2011-09-28 株式会社東芝 暗号化／復号装置
KR100837270B1 (ko) * 2006-06-07 2008-06-11 삼성전자주식회사 스마트 카드 및 그것의 데이터 보안 방법
US7921148B2 (en) * 2006-08-09 2011-04-05 Infineon Technologies Ag Standard cell for arithmetic logic unit and chip card controller
US20100281092A1 (en) * 2006-08-09 2010-11-04 Thomas Kuenemund Standard cell for arithmetic logic unit and chip card controller
KR101566408B1 (ko) * 2009-03-13 2015-11-05 삼성전자주식회사 불 마스크와 산술 마스크의 변환 회로 및 변환 방법
US8392494B2 (en) * 2009-06-26 2013-03-05 Intel Corporation Method and apparatus for performing efficient side-channel attack resistant reduction using montgomery or barrett reduction
WO2012127572A1 (fr) 2011-03-18 2012-09-27 富士通株式会社 Procédé, programme et dispositif de traitement de données secrètes
WO2013081588A1 (fr) * 2011-11-30 2013-06-06 Intel Corporation Instruction et logique destinées à donner une fonctionnalité de comparaison horizontale sur un vecteur
US9588764B2 (en) 2011-12-23 2017-03-07 Intel Corporation Apparatus and method of improved extract instructions
US9542154B2 (en) * 2013-06-25 2017-01-10 Intel Corporation Fused multiply add operations using bit masks
EP2884387B1 (fr) * 2013-12-13 2016-09-14 Thomson Licensing Ajout modulaire efficace résistant aux attaques par canaux auxiliaires
US9898623B2 (en) 2014-03-31 2018-02-20 Stmicroelectronics S.R.L. Method for performing an encryption with look-up tables, and corresponding encryption apparatus and computer program product
EP3424175B1 (fr) 2016-03-03 2024-02-21 Cryptography Research, Inc. Conversion d'une valeur masquée booléenne en une valeur masquée arithmétiquement pour des opérations cryptographiques
EP3503460B1 (fr) * 2017-12-22 2025-09-03 Secure-IC SAS Système et procédé d'addition arithmétique de données avec masque booléen
EP3557813A1 (fr) 2018-04-17 2019-10-23 Gemalto Sa Procédé protégé contre les attaques par canaux auxiliaires effectuant une opération arithmétique d'un algorithme cryptographique mélangeant des opérations booléennes et arithmétiques
DE102018113475A1 (de) 2018-06-06 2019-12-12 Infineon Technologies Ag Rechenwerk zum rechnen mit maskierten daten
US11507699B2 (en) 2019-09-27 2022-11-22 Intel Corporation Processor with private pipeline
FR3101980B1 (fr) 2019-10-11 2021-12-10 St Microelectronics Grenoble 2 Processeur
FR3101982B1 (fr) 2019-10-11 2024-03-08 St Microelectronics Grenoble 2 Détermination d'un bit indicateur
FR3101981B1 (fr) 2019-10-11 2021-11-12 St Microelectronics Grenoble 2 Extraction et insertion de mots binaires

Also Published As

Publication number Publication date
US20210109708A1 (en) 2021-04-15
CN112653448B (zh) 2025-07-04
US11714604B2 (en) 2023-08-01
CN112653448A (zh) 2021-04-13
FR3101983A1 (fr) 2021-04-16

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