ATE395807T1 - Parallelebenensubstrat - Google Patents

Parallelebenensubstrat

Info

Publication number
ATE395807T1
ATE395807T1 AT01989795T AT01989795T ATE395807T1 AT E395807 T1 ATE395807 T1 AT E395807T1 AT 01989795 T AT01989795 T AT 01989795T AT 01989795 T AT01989795 T AT 01989795T AT E395807 T1 ATE395807 T1 AT E395807T1
Authority
AT
Austria
Prior art keywords
parallel plane
plane substrate
conductive material
dielectric material
layers
Prior art date
Application number
AT01989795T
Other languages
English (en)
Inventor
Robert Sankman
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE395807T1 publication Critical patent/ATE395807T1/de

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1028—Thin metal strips as connectors or conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0235—Laminating followed by cutting or slicing perpendicular to plane of the laminate; Embedding wires in an object and cutting or slicing the object perpendicular to direction of the wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Bipolar Transistors (AREA)
  • Inorganic Insulating Materials (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Recrystallisation Techniques (AREA)
AT01989795T 2000-12-19 2001-11-15 Parallelebenensubstrat ATE395807T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/741,206 US6563210B2 (en) 2000-12-19 2000-12-19 Parallel plane substrate

Publications (1)

Publication Number Publication Date
ATE395807T1 true ATE395807T1 (de) 2008-05-15

Family

ID=24979788

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01989795T ATE395807T1 (de) 2000-12-19 2001-11-15 Parallelebenensubstrat

Country Status (10)

Country Link
US (2) US6563210B2 (de)
EP (1) EP1344435B1 (de)
JP (1) JP2004527898A (de)
KR (1) KR100550298B1 (de)
CN (1) CN1543757A (de)
AT (1) ATE395807T1 (de)
AU (1) AU2002228674A1 (de)
DE (1) DE60134042D1 (de)
MY (1) MY123629A (de)
WO (1) WO2002051222A2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW566796U (en) * 2003-03-12 2003-12-11 Unimicron Technology Corp Standard printed circuit board core
US7566960B1 (en) * 2003-10-31 2009-07-28 Xilinx, Inc. Interposing structure
DE102004050476B3 (de) * 2004-10-16 2006-04-06 Infineon Technologies Ag Verfahren zum Herstellen einer Umverdrahtungs-Leiterplatte
CN101171895B (zh) * 2005-06-30 2010-06-23 揖斐电株式会社 印刷线路板
JP5021472B2 (ja) * 2005-06-30 2012-09-05 イビデン株式会社 プリント配線板の製造方法
TWI382502B (zh) * 2007-12-02 2013-01-11 龍華科技大學 晶片封裝之結構改良
JP5257518B2 (ja) * 2009-08-28 2013-08-07 株式会社村田製作所 基板製造方法および樹脂基板
US8963013B2 (en) 2010-12-07 2015-02-24 Masud Beroz Three dimensional interposer device
FR2976720A1 (fr) * 2011-06-15 2012-12-21 St Microelectronics Sa Procede de connexion electrique entre des elements d'une structure integree tridimensionnelle, et dispositif correspondant
US20130319759A1 (en) * 2012-05-31 2013-12-05 General Electric Company Fine-pitch flexible wiring
US10003149B2 (en) 2014-10-25 2018-06-19 ComponentZee, LLC Fluid pressure activated electrical contact devices and methods
US9583426B2 (en) * 2014-11-05 2017-02-28 Invensas Corporation Multi-layer substrates suitable for interconnection between circuit modules
US10025047B1 (en) 2017-04-14 2018-07-17 Google Llc Integration of silicon photonics IC for high data rate

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1765083A1 (de) 1968-03-29 1971-07-01 Siemens Ag Verfahren zum Herstellen von Traegern zum Aufnehmen und Verbinden elektrischer Bauelemente
DE1930642A1 (de) 1969-06-18 1971-01-07 Siemens Ag Leiterplatte zum Aufnehmen und Verbinden elektrischer Bauelemente
JPS5987893A (ja) 1982-11-12 1984-05-21 株式会社日立製作所 配線基板とその製造方法およびそれを用いた半導体装置
DE3709770A1 (de) 1987-03-25 1988-10-13 Ant Nachrichtentech Leiterplatte, -folie, multilayerinnenlage oder leitersubstrat mit durchkontaktierungen und herstellungsverfahren
JPH01124296A (ja) 1987-11-09 1989-05-17 Hitachi Chem Co Ltd 配線板の製造法
US5363275A (en) * 1993-02-10 1994-11-08 International Business Machines Corporation Modular component computer system
JP3684239B2 (ja) * 1995-01-10 2005-08-17 株式会社 日立製作所 低ｅｍｉ電子機器
JPH10270809A (ja) 1997-03-28 1998-10-09 Hoya Corp 配線基板およびその製造方法
US6075427A (en) * 1998-01-23 2000-06-13 Lucent Technologies Inc. MCM with high Q overlapping resonator
JPH11233917A (ja) 1998-02-16 1999-08-27 Sumitomo Metal Electronics Devices Inc 積層基板の製造方法
EP1028607A1 (de) 1998-05-06 2000-08-16 Ngk Insulators, Ltd. Leiterplattenmaterial, verfahren zur herstellung des plattenmaterials und zwischenblockkörper für das plattenmaterial
US6165892A (en) * 1998-07-31 2000-12-26 Kulicke & Soffa Holdings, Inc. Method of planarizing thin film layers deposited over a common circuit base

Also Published As

Publication number Publication date
DE60134042D1 (de) 2008-06-26
AU2002228674A1 (en) 2002-07-01
WO2002051222A2 (en) 2002-06-27
KR20030064423A (ko) 2003-07-31
US20020074644A1 (en) 2002-06-20
WO2002051222A3 (en) 2003-02-06
JP2004527898A (ja) 2004-09-09
EP1344435B1 (de) 2008-05-14
MY123629A (en) 2006-05-31
EP1344435A2 (de) 2003-09-17
CN1543757A (zh) 2004-11-03
US6563210B2 (en) 2003-05-13
US6632734B2 (en) 2003-10-14
KR100550298B1 (ko) 2006-02-08
US20030127742A1 (en) 2003-07-10
HK1058283A1 (en) 2004-05-07

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Legal Events

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