ATE407429T1 - Bezüglich tastverhältnis effiziente sram- zellenprüfung - Google Patents

Bezüglich tastverhältnis effiziente sram- zellenprüfung

Info

Publication number
ATE407429T1
ATE407429T1 AT02787139T AT02787139T ATE407429T1 AT E407429 T1 ATE407429 T1 AT E407429T1 AT 02787139 T AT02787139 T AT 02787139T AT 02787139 T AT02787139 T AT 02787139T AT E407429 T1 ATE407429 T1 AT E407429T1
Authority
AT
Austria
Prior art keywords
wordlines
bitlines
memory cells
bitline
regard
Prior art date
Application number
AT02787139T
Other languages
English (en)
Inventor
Erik A Nelson
Harold Pilo
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE407429T1 publication Critical patent/ATE407429T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Photoreceptors In Electrophotography (AREA)
  • Reciprocating, Oscillating Or Vibrating Motors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT02787139T 2001-07-17 2002-07-11 Bezüglich tastverhältnis effiziente sram- zellenprüfung ATE407429T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/907,325 US6449200B1 (en) 2001-07-17 2001-07-17 Duty-cycle-efficient SRAM cell test

Publications (1)

Publication Number Publication Date
ATE407429T1 true ATE407429T1 (de) 2008-09-15

Family

ID=25423897

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02787139T ATE407429T1 (de) 2001-07-17 2002-07-11 Bezüglich tastverhältnis effiziente sram- zellenprüfung

Country Status (9)

Country Link
US (1) US6449200B1 (de)
EP (1) EP1415305B1 (de)
JP (1) JP4215637B2 (de)
KR (1) KR100558804B1 (de)
CN (1) CN100342457C (de)
AT (1) ATE407429T1 (de)
DE (1) DE60228731D1 (de)
TW (1) TW565850B (de)
WO (1) WO2003009304A2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6711076B2 (en) * 2002-07-26 2004-03-23 International Business Machines Corporation Active restore weak write test mode
CN100354636C (zh) * 2003-07-29 2007-12-12 华为技术有限公司 一种时钟占空比的测试方法及测试电路
US7142442B1 (en) * 2004-03-08 2006-11-28 Xilinx, Inc. Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability
GB0426005D0 (en) * 2004-11-26 2004-12-29 Koninkl Philips Electronics Nv Sram test method and sram test arrangement
KR100817061B1 (ko) * 2006-09-26 2008-03-27 삼성전자주식회사 기입 전류와 같은 방향의 금지 전류를 흐르게 하는마그네틱 램
US7505345B2 (en) * 2006-11-03 2009-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit and method for an SRAM with two phase word line pulse
US8270239B2 (en) * 2008-12-09 2012-09-18 Qualcomm Incorporated Semiconductor memory device and methods of performing a stress test on the semiconductor memory device
EP2502952B1 (de) 2009-11-19 2018-06-13 Toray Industries, Inc. Verfahren zur herstellung von polyamidimidharz-mikropartikeln
JP5610367B2 (ja) 2010-01-20 2014-10-22 株式会社リコー 中間転写ベルト及びそれを用いた電子写真装置
US8305835B2 (en) * 2010-12-14 2012-11-06 Advanced Micro Devices, Inc. Memory elements having configurable access duty cycles and related operating methods
US20120230740A1 (en) 2011-03-11 2012-09-13 Ricoh Company, Ltd. Intermediate transfer belt and image forming apparatus using the same
KR102003851B1 (ko) * 2012-08-31 2019-10-01 에스케이하이닉스 주식회사 메모리 및 이를 포함하는 메모리 시스템
US9281027B1 (en) * 2014-10-10 2016-03-08 Arm Limited Test techniques in memory devices
US9959912B2 (en) 2016-02-02 2018-05-01 Qualcomm Incorporated Timed sense amplifier circuits and methods in a semiconductor memory
TWI739494B (zh) * 2020-06-29 2021-09-11 華邦電子股份有限公司 感測放大裝置
CN113936730B (zh) * 2020-07-13 2022-10-14 长鑫存储技术有限公司 半导体芯片的测试方法、测试系统及测试设备
CN116779016A (zh) * 2022-03-11 2023-09-19 长鑫存储技术有限公司 存储器芯片的测试电路及测试方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4879690A (en) * 1987-09-07 1989-11-07 Mitsubishi Denki Kabushiki Kaisha Static random access memory with reduced soft error rate
JPH0756759B2 (ja) 1990-12-27 1995-06-14 株式会社東芝 スタティック型半導体記憶装置
US5424988A (en) 1992-09-30 1995-06-13 Sgs-Thomson Microelectronics, Inc. Stress test for memory arrays in integrated circuits
JP2885597B2 (ja) 1993-03-10 1999-04-26 株式会社東芝 半導体メモリ
US5477176A (en) 1994-06-02 1995-12-19 Motorola Inc. Power-on reset circuit for preventing multiple word line selections during power-up of an integrated circuit memory
DE69531092T2 (de) 1994-12-22 2004-04-01 Cypress Semiconductor Corp., San Jose Einseitige Simplex-Zweitorspeicherzelle
US5881010A (en) 1997-05-15 1999-03-09 Stmicroelectronics, Inc. Multiple transistor dynamic random access memory array architecture with simultaneous refresh of multiple memory cells during a read operation
US6081466A (en) 1998-10-30 2000-06-27 Stmicroelectronics, Inc. Stress test mode entry at power up for low/zero power memories
JPH11317097A (ja) 1999-02-12 1999-11-16 Toshiba Corp 半導体記憶装置
US6104650A (en) 1999-07-09 2000-08-15 Micron Technology, Inc. Sacrifice read test mode
US6208572B1 (en) 2000-06-12 2001-03-27 International Business Machines Corporation Semiconductor memory device having resistive bitline contact testing

Also Published As

Publication number Publication date
JP2004535648A (ja) 2004-11-25
KR20040010724A (ko) 2004-01-31
EP1415305A2 (de) 2004-05-06
WO2003009304A3 (en) 2003-11-20
EP1415305B1 (de) 2008-09-03
KR100558804B1 (ko) 2006-03-10
CN100342457C (zh) 2007-10-10
WO2003009304A2 (en) 2003-01-30
CN1518744A (zh) 2004-08-04
US6449200B1 (en) 2002-09-10
TW565850B (en) 2003-12-11
DE60228731D1 (en) 2008-10-16
JP4215637B2 (ja) 2009-01-28

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