ATE409910T1 - Signalaggregation - Google Patents

Signalaggregation

Info

Publication number
ATE409910T1
ATE409910T1 AT03752992T AT03752992T ATE409910T1 AT E409910 T1 ATE409910 T1 AT E409910T1 AT 03752992 T AT03752992 T AT 03752992T AT 03752992 T AT03752992 T AT 03752992T AT E409910 T1 ATE409910 T1 AT E409910T1
Authority
AT
Austria
Prior art keywords
channels
signal aggregation
memory
signal
establishing
Prior art date
Application number
AT03752992T
Other languages
English (en)
Inventor
Gilbert Wolrich
Mark Rosenbluth
Debra Bernstein
Myles Wilde
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE409910T1 publication Critical patent/ATE409910T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
  • Amplifiers (AREA)
  • Surgical Instruments (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Communication Control (AREA)
AT03752992T 2002-05-08 2003-05-02 Signalaggregation ATE409910T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/142,372 US7376950B2 (en) 2002-05-08 2002-05-08 Signal aggregation

Publications (1)

Publication Number Publication Date
ATE409910T1 true ATE409910T1 (de) 2008-10-15

Family

ID=29399884

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03752992T ATE409910T1 (de) 2002-05-08 2003-05-02 Signalaggregation

Country Status (7)

Country Link
US (1) US7376950B2 (de)
EP (1) EP1504349B1 (de)
AT (1) ATE409910T1 (de)
AU (1) AU2003269404A1 (de)
DE (1) DE60323828D1 (de)
TW (1) TWI315038B (de)
WO (1) WO2003098452A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
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US7599361B2 (en) * 2004-07-02 2009-10-06 P-Cube Ltd. Wire-speed packet management in a multi-pipeline network processor
US7277990B2 (en) 2004-09-30 2007-10-02 Sanjeev Jain Method and apparatus providing efficient queue descriptor memory access
US7418543B2 (en) 2004-12-21 2008-08-26 Intel Corporation Processor having content addressable memory with command ordering
US7555630B2 (en) 2004-12-21 2009-06-30 Intel Corporation Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit
US7467256B2 (en) 2004-12-28 2008-12-16 Intel Corporation Processor having content addressable memory for block-based queue structures
US7664127B1 (en) 2005-04-05 2010-02-16 Sun Microsystems, Inc. Method for resolving mutex contention in a network system
US20060236011A1 (en) * 2005-04-15 2006-10-19 Charles Narad Ring management
US20070245074A1 (en) * 2006-03-30 2007-10-18 Rosenbluth Mark B Ring with on-chip buffer for efficient message passing
US7926013B2 (en) * 2007-12-31 2011-04-12 Intel Corporation Validating continuous signal phase matching in high-speed nets routed as differential pairs
TWI425795B (zh) * 2010-07-29 2014-02-01 Univ Nat Chiao Tung 追蹤網路封包之處理程序的方法
US20120166686A1 (en) * 2010-12-22 2012-06-28 Joerg Hartung Method, apparatus and system for aggregating interrupts of a data transfer
GB2495959A (en) 2011-10-26 2013-05-01 Imagination Tech Ltd Multi-threaded memory access processor

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JP2526691B2 (ja) * 1990-03-02 1996-08-21 三菱電機株式会社 プログラマブルコントロ―ラの制御方法
AU2476192A (en) * 1991-08-16 1993-03-16 Multichip Technology High-performance dynamic memory system
WO1993018461A1 (en) * 1992-03-09 1993-09-16 Auspex Systems, Inc. High-performance non-volatile ram protected write cache accelerator system
IL105638A0 (en) * 1992-05-13 1993-09-22 Southwest Bell Tech Resources Storage controlling system and method for transferring information
US5689678A (en) * 1993-03-11 1997-11-18 Emc Corporation Distributed storage array system having a plurality of modular control units
US5463643A (en) * 1994-03-07 1995-10-31 Dell Usa, L.P. Redundant memory channel array configuration with data striping and error correction capabilities
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JPH08278916A (ja) * 1994-11-30 1996-10-22 Hitachi Ltd マルチチャネルメモリシステム、転送情報同期化方法及び信号転送回路
US5615392A (en) * 1995-05-05 1997-03-25 Apple Computer, Inc. Method and apparatus for consolidated buffer handling for computer device input/output
US6308248B1 (en) * 1996-12-31 2001-10-23 Compaq Computer Corporation Method and system for allocating memory space using mapping controller, page table and frame numbers
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Also Published As

Publication number Publication date
WO2003098452A1 (en) 2003-11-27
DE60323828D1 (de) 2008-11-13
EP1504349A1 (de) 2005-02-09
TWI315038B (en) 2009-09-21
TW200405167A (en) 2004-04-01
US7376950B2 (en) 2008-05-20
US20030212852A1 (en) 2003-11-13
AU2003269404A1 (en) 2003-12-02
EP1504349B1 (de) 2008-10-01

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Legal Events

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