ATE421167T1 - Verfahren zum ätzen einer schicht mittels hilfselementen - Google Patents
Verfahren zum ätzen einer schicht mittels hilfselementenInfo
- Publication number
- ATE421167T1 ATE421167T1 AT00962032T AT00962032T ATE421167T1 AT E421167 T1 ATE421167 T1 AT E421167T1 AT 00962032 T AT00962032 T AT 00962032T AT 00962032 T AT00962032 T AT 00962032T AT E421167 T1 ATE421167 T1 AT E421167T1
- Authority
- AT
- Austria
- Prior art keywords
- raised structure
- layer
- wafer
- adjacent
- patterned masking
- Prior art date
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00388—Etch mask forming
- B81C1/00404—Mask characterised by its size, orientation or shape
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00388—Etch mask forming
- B81C1/00412—Mask characterised by its behaviour during the etching process, e.g. soluble masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
- H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
- H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
- H10P50/694—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks or redeposited masks
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Drying Of Semiconductors (AREA)
- Micromachines (AREA)
- Weting (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/372,700 US6242363B1 (en) | 1999-08-11 | 1999-08-11 | Method of etching a wafer layer using a sacrificial wall to form vertical sidewall |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE421167T1 true ATE421167T1 (de) | 2009-01-15 |
Family
ID=23469272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT00962032T ATE421167T1 (de) | 1999-08-11 | 2000-08-01 | Verfahren zum ätzen einer schicht mittels hilfselementen |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US6242363B1 (de) |
| EP (1) | EP1221176B1 (de) |
| AT (1) | ATE421167T1 (de) |
| AU (1) | AU7390000A (de) |
| DE (1) | DE60041410D1 (de) |
| TW (1) | TW529057B (de) |
| WO (1) | WO2001011672A1 (de) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316282B1 (en) * | 1999-08-11 | 2001-11-13 | Adc Telecommunications, Inc. | Method of etching a wafer layer using multiple layers of the same photoresistant material |
| US6544898B2 (en) * | 2001-06-25 | 2003-04-08 | Adc Telecommunications, Inc. | Method for improved die release of a semiconductor device from a wafer |
| US6932934B2 (en) | 2002-07-11 | 2005-08-23 | Molecular Imprints, Inc. | Formation of discontinuous films during an imprint lithography process |
| US7077992B2 (en) | 2002-07-11 | 2006-07-18 | Molecular Imprints, Inc. | Step and repeat imprint lithography processes |
| US8349241B2 (en) | 2002-10-04 | 2013-01-08 | Molecular Imprints, Inc. | Method to arrange features on a substrate to replicate features having minimal dimensional variability |
| US7906058B2 (en) * | 2005-12-01 | 2011-03-15 | Molecular Imprints, Inc. | Bifurcated contact printing technique |
| US7803308B2 (en) | 2005-12-01 | 2010-09-28 | Molecular Imprints, Inc. | Technique for separating a mold from solidified imprinting material |
| US7670530B2 (en) | 2006-01-20 | 2010-03-02 | Molecular Imprints, Inc. | Patterning substrates employing multiple chucks |
| MY144847A (en) | 2005-12-08 | 2011-11-30 | Molecular Imprints Inc | Method and system for double-sided patterning of substrates |
| US8142850B2 (en) | 2006-04-03 | 2012-03-27 | Molecular Imprints, Inc. | Patterning a plurality of fields on a substrate to compensate for differing evaporation times |
| JP5306989B2 (ja) * | 2006-04-03 | 2013-10-02 | モレキュラー・インプリンツ・インコーポレーテッド | 複数のフィールド及びアライメント・マークを有する基板を同時にパターニングする方法 |
| US8850980B2 (en) | 2006-04-03 | 2014-10-07 | Canon Nanotechnologies, Inc. | Tessellated patterns in imprint lithography |
| US7802978B2 (en) | 2006-04-03 | 2010-09-28 | Molecular Imprints, Inc. | Imprinting of partial fields at the edge of the wafer |
| US8012395B2 (en) | 2006-04-18 | 2011-09-06 | Molecular Imprints, Inc. | Template having alignment marks formed of contrast material |
| US7547398B2 (en) | 2006-04-18 | 2009-06-16 | Molecular Imprints, Inc. | Self-aligned process for fabricating imprint templates containing variously etched features |
| CN113582130B (zh) * | 2021-07-27 | 2024-01-05 | 绍兴中芯集成电路制造股份有限公司 | 基于晶圆制备mems器件的方法 |
Family Cites Families (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2657378B2 (ja) | 1987-05-20 | 1997-09-24 | 日本テキサス・インスツルメンツ株式会社 | 光スイッチング装置 |
| US5420067A (en) * | 1990-09-28 | 1995-05-30 | The United States Of America As Represented By The Secretary Of The Navy | Method of fabricatring sub-half-micron trenches and holes |
| US5110760A (en) * | 1990-09-28 | 1992-05-05 | The United States Of America As Represented By The Secretary Of The Navy | Method of nanometer lithography |
| JPH0543399A (ja) | 1991-03-08 | 1993-02-23 | Ricoh Co Ltd | 薄膜機能部材 |
| US5148506A (en) | 1991-04-26 | 1992-09-15 | Texas Instruments Incorporated | Optical crossbar switch |
| US5155778A (en) | 1991-06-28 | 1992-10-13 | Texas Instruments Incorporated | Optical switch using spatial light modulators |
| US5232866A (en) * | 1991-10-23 | 1993-08-03 | International Business Machines Corporation | Isolated films using an air dielectric |
| US5199088A (en) | 1991-12-31 | 1993-03-30 | Texas Instruments Incorporated | Fiber optic switch with spatial light modulator device |
| JPH0621701A (ja) | 1992-06-30 | 1994-01-28 | Taiyo Yuden Co Ltd | 誘電体共振器を含むフィルタ装置 |
| US5239599A (en) | 1992-08-13 | 1993-08-24 | Jds Fitel Inc. | Moving fiber optical fiber switch |
| EP0683921B1 (de) | 1993-02-04 | 2004-06-16 | Cornell Research Foundation, Inc. | Mikrostrukturen und einzelmask, einkristall-herstellungsverfahren |
| US5616514A (en) * | 1993-06-03 | 1997-04-01 | Robert Bosch Gmbh | Method of fabricating a micromechanical sensor |
| US5345521A (en) | 1993-07-12 | 1994-09-06 | Texas Instrument Incorporated | Architecture for optical switch |
| JPH07106327A (ja) | 1993-10-06 | 1995-04-21 | Toshiba Corp | 半導体装置及びその製造方法 |
| US5618383A (en) * | 1994-03-30 | 1997-04-08 | Texas Instruments Incorporated | Narrow lateral dimensioned microelectronic structures and method of forming the same |
| WO1996016435A2 (en) | 1994-11-23 | 1996-05-30 | Philips Electronics N.V. | Semiconductor device provided with a microcomponent having a fixed and a movable electrode |
| US5594820A (en) | 1995-02-08 | 1997-01-14 | Jds Fitel Inc. | Opto-mechanical device having optical element movable by twin flexures |
| US5594818A (en) | 1995-03-08 | 1997-01-14 | Lucent Technologies Inc. | Digital optical switch and modulator and a method for digital optical switching and modulation |
| US5623564A (en) | 1995-06-07 | 1997-04-22 | Lucent Technologies Inc. | Self-aligned mechanical optical switch |
| FR2736934B1 (fr) * | 1995-07-21 | 1997-08-22 | Commissariat Energie Atomique | Procede de fabrication d'une structure avec une couche utile maintenue a distance d'un substrat par des butees, et de desolidarisation d'une telle couche |
| CA2156029C (en) | 1995-08-14 | 2000-02-29 | John O. Smiley | Optical switching device |
| US5705433A (en) * | 1995-08-24 | 1998-01-06 | Applied Materials, Inc. | Etching silicon-containing materials by use of silicon-containing compounds |
| US5623568A (en) | 1995-09-15 | 1997-04-22 | Lucent Technologies Inc. | Compact and fabrication tolerant high speed digital optical Y-switches |
| US5661591A (en) | 1995-09-29 | 1997-08-26 | Texas Instruments Incorporated | Optical switch having an analog beam for steering light |
| US5627924A (en) | 1996-01-18 | 1997-05-06 | Lucent Technologies Inc. | Article comprising a non-mechanical optical fiber switch |
| US5778513A (en) | 1996-02-09 | 1998-07-14 | Denny K. Miu | Bulk fabricated electromagnetic micro-relays/micro-switches and method of making same |
| US5684631A (en) | 1996-05-13 | 1997-11-04 | Lucent Technologies Inc. | Optical modulator/switch including reflective zone plate and related method of use |
| US5706123A (en) | 1996-09-27 | 1998-01-06 | Texas Instruments Incorporated | Switched control signals for digital micro-mirror device with split reset |
| US5774604A (en) | 1996-10-23 | 1998-06-30 | Texas Instruments Incorporated | Using an asymmetric element to create a 1XN optical switch |
| US5761350A (en) | 1997-01-22 | 1998-06-02 | Koh; Seungug | Method and apparatus for providing a seamless electrical/optical multi-layer micro-opto-electro-mechanical system assembly |
| US5790720A (en) | 1997-05-06 | 1998-08-04 | Lucent Technologies, Inc. | Acoustic-optic silica optical circuit switch |
| US5808780A (en) | 1997-06-09 | 1998-09-15 | Texas Instruments Incorporated | Non-contacting micromechanical optical switch |
-
1999
- 1999-08-11 US US09/372,700 patent/US6242363B1/en not_active Expired - Lifetime
-
2000
- 2000-08-01 AT AT00962032T patent/ATE421167T1/de not_active IP Right Cessation
- 2000-08-01 EP EP00962032A patent/EP1221176B1/de not_active Expired - Lifetime
- 2000-08-01 AU AU73900/00A patent/AU7390000A/en not_active Abandoned
- 2000-08-01 DE DE60041410T patent/DE60041410D1/de not_active Expired - Lifetime
- 2000-08-01 WO PCT/US2000/040533 patent/WO2001011672A1/en not_active Ceased
- 2000-10-13 TW TW089116107A patent/TW529057B/zh not_active IP Right Cessation
-
2001
- 2001-02-20 US US09/788,821 patent/US20010009777A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| EP1221176B1 (de) | 2009-01-14 |
| TW529057B (en) | 2003-04-21 |
| AU7390000A (en) | 2001-03-05 |
| US20010009777A1 (en) | 2001-07-26 |
| DE60041410D1 (de) | 2009-03-05 |
| EP1221176A2 (de) | 2002-07-10 |
| WO2001011672A1 (en) | 2001-02-15 |
| WO2001011672A8 (en) | 2001-06-14 |
| US6242363B1 (en) | 2001-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| ATE421167T1 (de) | Verfahren zum ätzen einer schicht mittels hilfselementen | |
| WO2000014797A3 (en) | Isolation region forming methods | |
| TW200621622A (en) | Semiconductor methods and structures background of the invention | |
| KR100282086B1 (ko) | 반도체 집적 회로 제조 방법 및 반도체 집적 회로 웨이퍼 제조방법 | |
| SG143176A1 (en) | Method and structure of pattern mask for dry etching | |
| US6383936B1 (en) | Method for removing black silicon in semiconductor fabrication | |
| JP2009188224A (ja) | 半導体装置の製造方法 | |
| KR20060015949A (ko) | 금속 패턴 형성 방법 | |
| KR100695434B1 (ko) | 반도체 소자의 미세 패턴 형성방법 | |
| KR0168148B1 (ko) | 반도체 소자의 필드 산화막 형성방법 | |
| JP2004303784A (ja) | 半導体装置の製造方法 | |
| KR950007056A (ko) | 반도체 소자의 소자격리 산화막 형성방법 | |
| KR100632627B1 (ko) | 반도체 소자의 제조방법 | |
| KR20060136174A (ko) | 미세 패턴 형성 방법 | |
| KR950011170B1 (ko) | 3층 레지스트를 이용한 게이트전극 형성방법 | |
| KR100202657B1 (ko) | 트랜지스터의 제조방법 | |
| KR100955929B1 (ko) | 반도체소자의 게이트 버퍼스페이서 형성방법 | |
| US7098103B2 (en) | Method and structure for non-single-polycrystalline capacitor in an integrated circuit | |
| KR0151618B1 (ko) | 폴리실리콘 패턴 형성방법 | |
| KR19980039342A (ko) | 반도체장치의 제조방법 | |
| KR20050096632A (ko) | 반도체소자의 형성방법 | |
| KR20070066111A (ko) | 반도체 소자의 미세 패턴 형성 방법 | |
| TW428226B (en) | Method for defining polysilicon pattern | |
| KR970052676A (ko) | 반도체 장치의 제조방법 | |
| KR20060075437A (ko) | 플래쉬 메모리소자의 게이트 산화막 형성방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |