ATE424060T1 - Codierung von informationen in integrierten schaltungen - Google Patents

Codierung von informationen in integrierten schaltungen

Info

Publication number
ATE424060T1
ATE424060T1 AT03795107T AT03795107T ATE424060T1 AT E424060 T1 ATE424060 T1 AT E424060T1 AT 03795107 T AT03795107 T AT 03795107T AT 03795107 T AT03795107 T AT 03795107T AT E424060 T1 ATE424060 T1 AT E424060T1
Authority
AT
Austria
Prior art keywords
signal
paths
path
produced
logic value
Prior art date
Application number
AT03795107T
Other languages
English (en)
Inventor
Francesco Pessolano
Dijk Victor Van
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE424060T1 publication Critical patent/ATE424060T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0266—Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G01R31/318538—Topological or mechanical aspects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Pulse Circuits (AREA)
AT03795107T 2002-09-13 2003-08-06 Codierung von informationen in integrierten schaltungen ATE424060T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02078779 2002-09-13

Publications (1)

Publication Number Publication Date
ATE424060T1 true ATE424060T1 (de) 2009-03-15

Family

ID=31985093

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03795107T ATE424060T1 (de) 2002-09-13 2003-08-06 Codierung von informationen in integrierten schaltungen

Country Status (10)

Country Link
US (1) US7515074B2 (de)
EP (1) EP1540828B1 (de)
JP (1) JP2005538632A (de)
KR (1) KR20050043945A (de)
CN (1) CN100481731C (de)
AT (1) ATE424060T1 (de)
AU (1) AU2003255884A1 (de)
DE (1) DE60326363D1 (de)
TW (1) TWI310594B (de)
WO (1) WO2004025838A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8145442B2 (en) * 2009-01-30 2012-03-27 Synopsys, Inc. Fast and accurate estimation of gate output loading

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3084223A (en) * 1960-12-23 1963-04-02 Bell Telephone Labor Inc Crosstalk reduction in plural carrier multiplex systems
JPS5140449A (ja) * 1974-10-04 1976-04-05 Toray Industries Makitorisochi
JPS5784149A (en) * 1980-11-14 1982-05-26 Hitachi Ltd Semiconductor integrated circuit device
JPS604347A (ja) * 1983-06-22 1985-01-10 Fuji Xerox Co Ltd デイジタル信号伝送システムの障害対策方式
US5493588A (en) * 1992-01-22 1996-02-20 Trimble Navigation Limited Multipath compensation for code phase signals
JP3136742B2 (ja) * 1992-02-14 2001-02-19 日産自動車株式会社 通信装置
IL120538A (en) * 1997-03-26 2000-11-21 Dspc Tech Ltd Method and apparatus for reducing spread-spectrum noise
US6148038A (en) * 1997-03-31 2000-11-14 Sun Microsystems, Inc. Circuit for detecting and decoding phase encoded digital serial data
US6480548B1 (en) * 1997-11-17 2002-11-12 Silicon Graphics, Inc. Spacial derivative bus encoder and decoder
BR9908637A (pt) * 1998-03-11 2000-11-14 Thomson Licensing Sa Sistema de modulação de sinal digital
JP3137328B2 (ja) * 1998-04-22 2001-02-19 富士通株式会社 ノイズ除去方法および伝送回路
US6731622B1 (en) * 1998-05-01 2004-05-04 Telefonaktiebolaget Lm Ericsson (Publ) Multipath propagation delay determining means using periodically inserted pilot symbols
JP2001326584A (ja) * 2000-05-18 2001-11-22 Nec Corp パス検出方式と受信装置
KR100335503B1 (ko) * 2000-06-26 2002-05-08 윤종용 서로 다른 지연 특성을 동일하게 하는 신호 전달 회로,신호 전달 방법 및 이를 구비하는 반도체 장치의 데이터래치 회로
JP3696812B2 (ja) * 2001-07-19 2005-09-21 富士通株式会社 入出力インタフェースおよび半導体集積回路
JP3813490B2 (ja) * 2001-10-30 2006-08-23 富士通株式会社 スペクトラム拡散レイク受信機
JP2003316736A (ja) * 2002-04-19 2003-11-07 Oki Electric Ind Co Ltd Ｕｓｂ回路およびデータ構造
US6958721B2 (en) * 2003-09-18 2005-10-25 The Regents Of The University Of Colorado Matched delay line voltage converter
JP3927576B2 (ja) * 2005-01-31 2007-06-13 富士通株式会社 入出力インタフェースおよび半導体集積回路
US20070271535A1 (en) * 2006-05-16 2007-11-22 National Tsing Hua University Method for crosstalk elimination and bus architecture performing the same

Also Published As

Publication number Publication date
TWI310594B (en) 2009-06-01
TW200419734A (en) 2004-10-01
JP2005538632A (ja) 2005-12-15
DE60326363D1 (de) 2009-04-09
EP1540828B1 (de) 2009-02-25
US7515074B2 (en) 2009-04-07
KR20050043945A (ko) 2005-05-11
WO2004025838A1 (en) 2004-03-25
US20050270194A1 (en) 2005-12-08
CN1682447A (zh) 2005-10-12
CN100481731C (zh) 2009-04-22
EP1540828A1 (de) 2005-06-15
AU2003255884A1 (en) 2004-04-30

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Legal Events

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