ATE433584T1 - Verfahren, system und programm zur handhabung von eingabe-/ausgabebefehlen - Google Patents

Verfahren, system und programm zur handhabung von eingabe-/ausgabebefehlen

Info

Publication number
ATE433584T1
ATE433584T1 AT03765941T AT03765941T ATE433584T1 AT E433584 T1 ATE433584 T1 AT E433584T1 AT 03765941 T AT03765941 T AT 03765941T AT 03765941 T AT03765941 T AT 03765941T AT E433584 T1 ATE433584 T1 AT E433584T1
Authority
AT
Austria
Prior art keywords
target device
program
initiator
handling input
bus
Prior art date
Application number
AT03765941T
Other languages
English (en)
Inventor
David Smith
Sailesh Bissessur
Richard Mackey
Mark Schmisseur
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE433584T1 publication Critical patent/ATE433584T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Programmable Controllers (AREA)
AT03765941T 2002-07-24 2003-07-23 Verfahren, system und programm zur handhabung von eingabe-/ausgabebefehlen ATE433584T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/205,663 US7130933B2 (en) 2002-07-24 2002-07-24 Method, system, and program for handling input/output commands
PCT/US2003/022941 WO2004010316A2 (en) 2002-07-24 2003-07-23 Method, system, and program for handling input/output commands

Publications (1)

Publication Number Publication Date
ATE433584T1 true ATE433584T1 (de) 2009-06-15

Family

ID=30770115

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03765941T ATE433584T1 (de) 2002-07-24 2003-07-23 Verfahren, system und programm zur handhabung von eingabe-/ausgabebefehlen

Country Status (8)

Country Link
US (2) US7130933B2 (de)
EP (1) EP1573559B1 (de)
CN (1) CN100481043C (de)
AT (1) ATE433584T1 (de)
AU (1) AU2003259210A1 (de)
DE (1) DE60327945D1 (de)
TW (1) TWI298838B (de)
WO (1) WO2004010316A2 (de)

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US8161480B2 (en) * 2007-05-29 2012-04-17 International Business Machines Corporation Performing an allreduce operation using shared memory
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US7991857B2 (en) 2008-03-24 2011-08-02 International Business Machines Corporation Broadcasting a message in a parallel computer
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US8484440B2 (en) 2008-05-21 2013-07-09 International Business Machines Corporation Performing an allreduce operation on a plurality of compute nodes of a parallel computer
US8375197B2 (en) * 2008-05-21 2013-02-12 International Business Machines Corporation Performing an allreduce operation on a plurality of compute nodes of a parallel computer
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US8332460B2 (en) 2010-04-14 2012-12-11 International Business Machines Corporation Performing a local reduction operation on a parallel computer
US9424087B2 (en) 2010-04-29 2016-08-23 International Business Machines Corporation Optimizing collective operations
US8346883B2 (en) 2010-05-19 2013-01-01 International Business Machines Corporation Effecting hardware acceleration of broadcast operations in a parallel computer
US8489859B2 (en) 2010-05-28 2013-07-16 International Business Machines Corporation Performing a deterministic reduction operation in a compute node organized into a branched tree topology
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US8713379B2 (en) * 2011-02-08 2014-04-29 Diablo Technologies Inc. System and method of interfacing co-processors and input/output devices via a main memory system
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US8893083B2 (en) 2011-08-09 2014-11-18 International Business Machines Coporation Collective operation protocol selection in a parallel computer
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Also Published As

Publication number Publication date
US7130933B2 (en) 2006-10-31
TW200406680A (en) 2004-05-01
CN1864145A (zh) 2006-11-15
TWI298838B (en) 2008-07-11
EP1573559A2 (de) 2005-09-14
US7464199B2 (en) 2008-12-09
US20040019711A1 (en) 2004-01-29
EP1573559B1 (de) 2009-06-10
US20060168359A1 (en) 2006-07-27
CN100481043C (zh) 2009-04-22
WO2004010316A3 (en) 2004-05-27
WO2004010316A2 (en) 2004-01-29
DE60327945D1 (de) 2009-07-23
AU2003259210A1 (en) 2004-02-09

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