ATE436029T1 - Analog-ic mit testanordnung und testverfahren für ein solches ic - Google Patents

Analog-ic mit testanordnung und testverfahren für ein solches ic

Info

Publication number
ATE436029T1
ATE436029T1 AT06809664T AT06809664T ATE436029T1 AT E436029 T1 ATE436029 T1 AT E436029T1 AT 06809664 T AT06809664 T AT 06809664T AT 06809664 T AT06809664 T AT 06809664T AT E436029 T1 ATE436029 T1 AT E436029T1
Authority
AT
Austria
Prior art keywords
analog
stages
test
signal path
analog stages
Prior art date
Application number
AT06809664T
Other languages
English (en)
Inventor
Amir Zjajo
Hendrik Bergveld
Rodger Schuttert
De Gyvez Jose De Jesus Pineda
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE436029T1 publication Critical patent/ATE436029T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/3167—Testing of combined analog and digital circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31721—Power aspects, e.g. power supplies for test circuits, power saving during test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318575—Power distribution; Power saving

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
AT06809664T 2005-10-26 2006-10-20 Analog-ic mit testanordnung und testverfahren für ein solches ic ATE436029T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05110048 2005-10-26
PCT/IB2006/053878 WO2007049210A2 (en) 2005-10-26 2006-10-20 Analog ic having test arrangement and test method for such an ic

Publications (1)

Publication Number Publication Date
ATE436029T1 true ATE436029T1 (de) 2009-07-15

Family

ID=37905620

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06809664T ATE436029T1 (de) 2005-10-26 2006-10-20 Analog-ic mit testanordnung und testverfahren für ein solches ic

Country Status (8)

Country Link
US (1) US7671618B2 (de)
EP (1) EP1943534B1 (de)
JP (1) JP2009513968A (de)
KR (1) KR20080069647A (de)
CN (1) CN101297209B (de)
AT (1) ATE436029T1 (de)
DE (1) DE602006007726D1 (de)
WO (1) WO2007049210A2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7812628B2 (en) * 2006-12-13 2010-10-12 Renesas Electronics Corporation Method of on-chip current measurement and semiconductor IC
US20090039897A1 (en) * 2007-08-10 2009-02-12 Via Technologies, Inc. Systems and Methods for Scan Chain Testing Using Analog Signals
US8217673B2 (en) * 2009-09-02 2012-07-10 Freescale Semiconductor, Inc. Method and circuit for testing integrated circuit
US8589750B2 (en) * 2010-07-14 2013-11-19 Qualcomm, Incorporated Methods and apparatus for providing a built-in self test
US9110142B2 (en) * 2011-09-30 2015-08-18 Freescale Semiconductor, Inc. Methods and apparatus for testing multiple-IC devices
US8887017B2 (en) * 2012-10-12 2014-11-11 Freescale Semiconductor, Inc. Processor switchable between test and debug modes
WO2016146168A1 (en) * 2015-03-17 2016-09-22 Huawei Technologies Co., Ltd. Mixed-signal integrated circuit
US11067623B2 (en) * 2019-05-19 2021-07-20 Test Research, Inc. Test system and method of operating the same
US20200410153A1 (en) 2019-05-30 2020-12-31 Celera, Inc. Automated circuit generation
CN111372018B (zh) * 2020-03-19 2021-06-15 成都微光集电科技有限公司 一种使用复位信号驱动电路的adc及图像传感器
US11342914B2 (en) * 2020-06-19 2022-05-24 Juniper Networks, Inc. Integrated circuit having state machine-driven flops in wrapper chains for device testing
US12556168B2 (en) 2021-04-13 2026-02-17 Mitsubishi Electric Corporation Semiconductor integrated circuit and semiconductor device
US20230076736A1 (en) * 2021-08-24 2023-03-09 Cilag Gmbh International Automatic remote center of motion adjustment for robotically controlled uterine manipulator

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5793778A (en) * 1997-04-11 1998-08-11 National Semiconductor Corporation Method and apparatus for testing analog and digital circuitry within a larger circuit
US5923097A (en) * 1997-07-24 1999-07-13 International Business Machines Corporation Switching supply test mode for analog cores
AU4061200A (en) * 1999-03-31 2000-10-16 Regents Of The University Of California, The Multi-channel detector readout method and integrated circuit
JP2002094368A (ja) * 2000-09-18 2002-03-29 Mitsubishi Electric Corp 半導体集積回路装置

Also Published As

Publication number Publication date
JP2009513968A (ja) 2009-04-02
US20090134904A1 (en) 2009-05-28
EP1943534A2 (de) 2008-07-16
CN101297209A (zh) 2008-10-29
KR20080069647A (ko) 2008-07-28
WO2007049210A3 (en) 2007-07-26
WO2007049210A2 (en) 2007-05-03
CN101297209B (zh) 2011-03-16
US7671618B2 (en) 2010-03-02
DE602006007726D1 (de) 2009-08-20
EP1943534B1 (de) 2009-07-08

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Legal Events

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