ATE535997T1 - Vorrichtung zum sichern der konfiguration von endgeräten eines integrierten schaltkreises und verfahren zur aktivierung dieser vorrichtung - Google Patents

Vorrichtung zum sichern der konfiguration von endgeräten eines integrierten schaltkreises und verfahren zur aktivierung dieser vorrichtung

Info

Publication number
ATE535997T1
ATE535997T1 AT09164952T AT09164952T ATE535997T1 AT E535997 T1 ATE535997 T1 AT E535997T1 AT 09164952 T AT09164952 T AT 09164952T AT 09164952 T AT09164952 T AT 09164952T AT E535997 T1 ATE535997 T1 AT E535997T1
Authority
AT
Austria
Prior art keywords
integrated circuit
activating
securing
configuration
terminal devices
Prior art date
Application number
AT09164952T
Other languages
English (en)
Inventor
Yves Theoduloz
Hugo Jaeggi
Lubomir Plavec
Original Assignee
Em Microelectronic Marin Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Em Microelectronic Marin Sa filed Critical Em Microelectronic Marin Sa
Application granted granted Critical
Publication of ATE535997T1 publication Critical patent/ATE535997T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017581—Coupling arrangements; Interface arrangements programmable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
AT09164952T 2008-07-17 2009-07-08 Vorrichtung zum sichern der konfiguration von endgeräten eines integrierten schaltkreises und verfahren zur aktivierung dieser vorrichtung ATE535997T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP08160648A EP2146432A1 (de) 2008-07-17 2008-07-17 Vorrichtung zum Sichern der Konfiguration von Endgeräten eines integrierten Schaltkreises und Verfahren zur Aktivierung dieser Vorrichtung

Publications (1)

Publication Number Publication Date
ATE535997T1 true ATE535997T1 (de) 2011-12-15

Family

ID=39967772

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09164952T ATE535997T1 (de) 2008-07-17 2009-07-08 Vorrichtung zum sichern der konfiguration von endgeräten eines integrierten schaltkreises und verfahren zur aktivierung dieser vorrichtung

Country Status (3)

Country Link
US (1) US7772886B2 (de)
EP (2) EP2146432A1 (de)
AT (1) ATE535997T1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9760137B2 (en) * 2014-03-29 2017-09-12 Intel Corporation Programmable scalable voltage translator
US10027325B1 (en) * 2017-06-28 2018-07-17 Texas Instruments Incorporated Circuit having a parallel voltage threshold architecture to support a wide voltage supply range
US10686438B2 (en) * 2017-08-29 2020-06-16 Taiwan Semiconductor Manufacturing Co., Ltd. Glitch preventing input/output circuits
DE102018110561B4 (de) 2017-08-29 2026-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Störimpuls-verhindernde Eingabe-/Ausgabe-Schaltungen und Verfahren zu deren Betrieb

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000228627A (ja) * 1999-02-05 2000-08-15 Mitsubishi Electric Corp 入出力回路
US6323687B1 (en) * 2000-11-03 2001-11-27 Fujitsu Limited Output drivers for integrated-circuit chips with VCCQ supply compensation
US6559690B2 (en) * 2001-03-15 2003-05-06 Micron Technology, Inc. Programmable dual drive strength output buffer with a shared boot circuit
US6882200B2 (en) * 2001-07-23 2005-04-19 Intel Corporation Controlling signal states and leakage current during a sleep mode
JP2003295988A (ja) 2002-04-05 2003-10-17 Matsushita Electric Ind Co Ltd 半導体装置
US6980035B1 (en) * 2003-03-18 2005-12-27 Xilinx, Inc. Auto-detect level shifter for multiple output voltage standards
KR100599216B1 (ko) * 2005-07-11 2006-07-12 삼성전자주식회사 반도체 메모리 장치의 출력회로 및 데이터 출력방법
US8970272B2 (en) * 2008-05-15 2015-03-03 Qualcomm Incorporated High-speed low-power latches

Also Published As

Publication number Publication date
EP2146433A3 (de) 2011-01-05
EP2146432A1 (de) 2010-01-20
US7772886B2 (en) 2010-08-10
US20100013518A1 (en) 2010-01-21
EP2146433A2 (de) 2010-01-20
EP2146433B1 (de) 2011-11-30

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