ATE443268T1 - Prüfung einer schaltung mit asynchronem zeitgeber - Google Patents

Prüfung einer schaltung mit asynchronem zeitgeber

Info

Publication number
ATE443268T1
ATE443268T1 AT05784826T AT05784826T ATE443268T1 AT E443268 T1 ATE443268 T1 AT E443268T1 AT 05784826 T AT05784826 T AT 05784826T AT 05784826 T AT05784826 T AT 05784826T AT E443268 T1 ATE443268 T1 AT E443268T1
Authority
AT
Austria
Prior art keywords
test
feedback loop
shift register
circuit
timing circuit
Prior art date
Application number
AT05784826T
Other languages
English (en)
Inventor
Adrianus Peeters
Beest Frank Te
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE443268T1 publication Critical patent/ATE443268T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Electronic Switches (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AT05784826T 2004-08-03 2005-07-21 Prüfung einer schaltung mit asynchronem zeitgeber ATE443268T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04103731 2004-08-03
PCT/IB2005/052455 WO2006013524A1 (en) 2004-08-03 2005-07-21 Testing of a circuit that has an asynchronous timing circuit

Publications (1)

Publication Number Publication Date
ATE443268T1 true ATE443268T1 (de) 2009-10-15

Family

ID=35431121

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05784826T ATE443268T1 (de) 2004-08-03 2005-07-21 Prüfung einer schaltung mit asynchronem zeitgeber

Country Status (7)

Country Link
US (1) US20080288837A1 (de)
EP (1) EP1776596B1 (de)
JP (1) JP2008509388A (de)
CN (1) CN1993626A (de)
AT (1) ATE443268T1 (de)
DE (1) DE602005016687D1 (de)
WO (1) WO2006013524A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009007906A1 (en) * 2007-07-10 2009-01-15 Koninklijke Philips Electronics N.V. Circuitry for synchronous testing of an asynchronous logic module
WO2009060259A1 (en) * 2007-11-06 2009-05-14 Koninklijke Philips Electronics, N.V. Testing of a circuit that has an asynchronous timing circuit
WO2010001187A1 (en) * 2008-06-30 2010-01-07 John Bainbridge Circuit to provide testability to a self-timed circuit
WO2011158500A1 (ja) 2010-06-17 2011-12-22 国立大学法人 奈良先端科学技術大学院大学 スキャン非同期記憶素子およびそれを備えた半導体集積回路ならびにその設計方法およびテストパターン生成方法
EP3118853B1 (de) 2011-06-27 2018-06-06 Thin Film Electronics ASA Kurzschlussreduktion bei einer elektronischen komponente mit einem auf einem flexiblen substrat angeordneten schichtstapel
US9412705B2 (en) 2011-06-27 2016-08-09 Thin Film Electronics Asa Short circuit reduction in a ferroelectric memory cell comprising a stack of layers arranged on a flexible substrate
CN102313871B (zh) * 2011-09-09 2013-09-18 山东华芯半导体有限公司 总线式测试节点链系统
US10884058B2 (en) * 2017-04-18 2021-01-05 Cryptography Research, Inc. Self-test of an asynchronous circuit
GB202304357D0 (en) * 2023-03-24 2023-05-10 Nordic Semiconductor Asa Circuit testing

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761695A (en) * 1972-10-16 1973-09-25 Ibm Method of level sensitive testing a functional logic system
US4698588A (en) * 1985-10-23 1987-10-06 Texas Instruments Incorporated Transparent shift register latch for isolating peripheral ports during scan testing of a logic circuit
US5239213A (en) * 1990-04-30 1993-08-24 Advanced Micro Devices, Inc. Precision timing control programmable logic device
US5365125A (en) * 1992-07-23 1994-11-15 Xilinx, Inc. Logic cell for field programmable gate array having optional internal feedback and optional cascade
US5896046A (en) * 1997-01-27 1999-04-20 International Business Machines Corporation Latch structure for ripple domino logic
US6918074B2 (en) * 2002-06-28 2005-07-12 Intel Corporation At speed testing asynchronous signals
US7436917B2 (en) * 2004-07-29 2008-10-14 Hewlett-Packard Development Company, L.P. Controller for clock synchronizer

Also Published As

Publication number Publication date
WO2006013524B1 (en) 2006-04-27
JP2008509388A (ja) 2008-03-27
WO2006013524A1 (en) 2006-02-09
US20080288837A1 (en) 2008-11-20
DE602005016687D1 (de) 2009-10-29
EP1776596A1 (de) 2007-04-25
EP1776596B1 (de) 2009-09-16
CN1993626A (zh) 2007-07-04

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Legal Events

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