ATE443926T1 - Verfahren zur herstellung eines halbleiterbauelementes - Google Patents

Verfahren zur herstellung eines halbleiterbauelementes

Info

Publication number
ATE443926T1
ATE443926T1 AT01911633T AT01911633T ATE443926T1 AT E443926 T1 ATE443926 T1 AT E443926T1 AT 01911633 T AT01911633 T AT 01911633T AT 01911633 T AT01911633 T AT 01911633T AT E443926 T1 ATE443926 T1 AT E443926T1
Authority
AT
Austria
Prior art keywords
layer
sub
semiconductor body
recess
conductivity type
Prior art date
Application number
AT01911633T
Other languages
English (en)
Inventor
Youri Ponomarev
Marian Webster
Charles Dachs
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE443926T1 publication Critical patent/ATE443926T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0218—Manufacture or treatment of FETs having insulated gates [IGFET] having pocket halo regions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
    • H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Glass Compositions (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
AT01911633T 2000-02-17 2001-02-09 Verfahren zur herstellung eines halbleiterbauelementes ATE443926T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP00200540 2000-02-17
EP00200738 2000-03-02
PCT/EP2001/001503 WO2001061741A1 (en) 2000-02-17 2001-02-09 A method of manufacturing a semiconductor device

Publications (1)

Publication Number Publication Date
ATE443926T1 true ATE443926T1 (de) 2009-10-15

Family

ID=26071854

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01911633T ATE443926T1 (de) 2000-02-17 2001-02-09 Verfahren zur herstellung eines halbleiterbauelementes

Country Status (8)

Country Link
US (1) US6544851B2 (de)
EP (1) EP1186020B1 (de)
JP (1) JP2003523626A (de)
KR (1) KR100697894B1 (de)
AT (1) ATE443926T1 (de)
DE (1) DE60139972D1 (de)
TW (1) TW506079B (de)
WO (1) WO2001061741A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6774001B2 (en) * 1998-10-13 2004-08-10 Stmicroelectronics, Inc. Self-aligned gate and method
KR100701369B1 (ko) * 2002-12-30 2007-03-28 동부일렉트로닉스 주식회사 트랜지스터 및 그 제조 방법
DE10333776B4 (de) * 2003-07-24 2005-06-30 Infineon Technologies Ag Verfahren zur Herstellung einer Gate-Struktur eines FETs
JP2007165541A (ja) * 2005-12-13 2007-06-28 Oki Electric Ind Co Ltd 半導体装置の製造方法
KR100869359B1 (ko) * 2006-09-28 2008-11-19 주식회사 하이닉스반도체 반도체 소자의 리세스 게이트 제조 방법
CN102087979A (zh) * 2009-12-04 2011-06-08 中国科学院微电子研究所 高性能半导体器件及其形成方法
US8436404B2 (en) 2009-12-30 2013-05-07 Intel Corporation Self-aligned contacts
JP2012038749A (ja) * 2010-08-03 2012-02-23 Elpida Memory Inc 半導体装置およびその製造方法
US9076817B2 (en) * 2011-08-04 2015-07-07 International Business Machines Corporation Epitaxial extension CMOS transistor
US9385044B2 (en) * 2012-12-31 2016-07-05 Texas Instruments Incorporated Replacement gate process
CN108630542B (zh) * 2017-03-17 2021-12-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4173818A (en) * 1978-05-30 1979-11-13 International Business Machines Corporation Method for fabricating transistor structures having very short effective channels
KR0140719B1 (ko) * 1995-03-08 1998-07-15 김주용 모스 전계효과 트랜지스터의 제조방법
US5534447A (en) * 1995-11-13 1996-07-09 United Microelectronics Corporation Process for fabricating MOS LDD transistor with pocket implant
US5899719A (en) * 1997-02-14 1999-05-04 United Semiconductor Corporation Sub-micron MOSFET
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
US5985726A (en) * 1998-11-06 1999-11-16 Advanced Micro Devices, Inc. Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET

Also Published As

Publication number Publication date
EP1186020B1 (de) 2009-09-23
TW506079B (en) 2002-10-11
WO2001061741A1 (en) 2001-08-23
US6544851B2 (en) 2003-04-08
EP1186020A1 (de) 2002-03-13
KR100697894B1 (ko) 2007-03-20
KR20010110768A (ko) 2001-12-13
DE60139972D1 (de) 2009-11-05
US20010016392A1 (en) 2001-08-23
JP2003523626A (ja) 2003-08-05

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