ATE445220T1 - Schaltung und verfahren zur verbesserung des nutzungsgrades in einem rasterpufferspeicher unter verwendung von fehlerhaften speicherstellen - Google Patents

Schaltung und verfahren zur verbesserung des nutzungsgrades in einem rasterpufferspeicher unter verwendung von fehlerhaften speicherstellen

Info

Publication number
ATE445220T1
ATE445220T1 AT02028177T AT02028177T ATE445220T1 AT E445220 T1 ATE445220 T1 AT E445220T1 AT 02028177 T AT02028177 T AT 02028177T AT 02028177 T AT02028177 T AT 02028177T AT E445220 T1 ATE445220 T1 AT E445220T1
Authority
AT
Austria
Prior art keywords
buffer memory
circuit
storage locations
memory
improving utilization
Prior art date
Application number
AT02028177T
Other languages
English (en)
Inventor
Shrjie Tzeng
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE445220T1 publication Critical patent/ATE445220T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G11C29/883—Masking faults in memories by using spares or by reconfiguring with partially good memories using a single defective memory device with reduced capacity, e.g. half capacity
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1208—Error catch memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
AT02028177T 2001-12-31 2002-12-19 Schaltung und verfahren zur verbesserung des nutzungsgrades in einem rasterpufferspeicher unter verwendung von fehlerhaften speicherstellen ATE445220T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/032,063 US6928588B2 (en) 2001-12-31 2001-12-31 System and method of improving memory yield in frame buffer memory using failing memory location

Publications (1)

Publication Number Publication Date
ATE445220T1 true ATE445220T1 (de) 2009-10-15

Family

ID=21862897

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02028177T ATE445220T1 (de) 2001-12-31 2002-12-19 Schaltung und verfahren zur verbesserung des nutzungsgrades in einem rasterpufferspeicher unter verwendung von fehlerhaften speicherstellen

Country Status (4)

Country Link
US (2) US6928588B2 (de)
EP (1) EP1324349B1 (de)
AT (1) ATE445220T1 (de)
DE (1) DE60233925D1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7930592B2 (en) * 2002-12-16 2011-04-19 International Business Machines Corporation Enabling memory redundancy during testing
JP2006114149A (ja) * 2004-10-15 2006-04-27 Fujitsu Ltd 半導体試験システム
JP2008033995A (ja) * 2006-07-26 2008-02-14 Matsushita Electric Ind Co Ltd メモリシステム
US20080083982A1 (en) * 2006-10-10 2008-04-10 International Business Machines Corporation Method and system for initiating proximity warning alarm for electronic devices and prohibiting operation thereof
US7856577B2 (en) * 2007-11-21 2010-12-21 Lsi Corporation Command language for memory testing
US7882406B2 (en) 2008-05-09 2011-02-01 Lsi Corporation Built in test controller with a downloadable testing program
US8934311B2 (en) 2011-09-06 2015-01-13 Samsung Electronics Co., Ltd. Semiconductor memory device capable of screening a weak bit and repairing the same
US8929167B2 (en) 2013-01-31 2015-01-06 Qualcomm Incorporated MRAM self-repair with BIST logic
US11461645B2 (en) * 2019-12-02 2022-10-04 International Business Machines Corporation Initialization of memory networks
KR102815309B1 (ko) * 2022-07-04 2025-05-30 주식회사 와이씨 버퍼 메모리의 확장 모드를 구현하는 반도체 테스트 장치

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5617531A (en) * 1993-11-02 1997-04-01 Motorola, Inc. Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor
US5502333A (en) * 1994-03-30 1996-03-26 International Business Machines Corporation Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
JP3274332B2 (ja) * 1995-11-29 2002-04-15 株式会社東芝 コントローラ・大容量メモリ混載型半導体集積回路装置およびそのテスト方法およびその使用方法、並びに半導体集積回路装置およびそのテスト方法
KR100268784B1 (ko) * 1997-06-26 2000-11-01 김영환 반도체 소자의 리던던트 장치
US6246680B1 (en) * 1997-06-30 2001-06-12 Sun Microsystems, Inc. Highly integrated multi-layer switch element architecture
US6011734A (en) * 1998-03-12 2000-01-04 Motorola, Inc. Fuseless memory repair system and method of operation
US6085334A (en) * 1998-04-17 2000-07-04 Motorola, Inc. Method and apparatus for testing an integrated memory device
JP3749789B2 (ja) * 1998-06-08 2006-03-01 株式会社東芝 半導体記憶装置
US6574763B1 (en) * 1999-12-28 2003-06-03 International Business Machines Corporation Method and apparatus for semiconductor integrated circuit testing and burn-in
US7076706B2 (en) * 2001-04-24 2006-07-11 International Business Machines Corporation Method and apparatus for ABIST diagnostics
US6763444B2 (en) * 2001-05-08 2004-07-13 Micron Technology, Inc. Read/write timing calibration of a memory array using a row or a redundant row

Also Published As

Publication number Publication date
EP1324349B1 (de) 2009-10-07
EP1324349A3 (de) 2007-01-03
US7313733B2 (en) 2007-12-25
US6928588B2 (en) 2005-08-09
EP1324349A2 (de) 2003-07-02
US20050268159A1 (en) 2005-12-01
US20030126512A1 (en) 2003-07-03
DE60233925D1 (de) 2009-11-19

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