ATE451718T1 - Herstellungsverfahren für halbleiterbauelemente mit silizidierten elektroden - Google Patents

Herstellungsverfahren für halbleiterbauelemente mit silizidierten elektroden

Info

Publication number
ATE451718T1
ATE451718T1 AT04077816T AT04077816T ATE451718T1 AT E451718 T1 ATE451718 T1 AT E451718T1 AT 04077816 T AT04077816 T AT 04077816T AT 04077816 T AT04077816 T AT 04077816T AT E451718 T1 ATE451718 T1 AT E451718T1
Authority
AT
Austria
Prior art keywords
layer
conductor
dielectric layer
semiconductor
metal layer
Prior art date
Application number
AT04077816T
Other languages
English (en)
Inventor
Tom Schram
Jacob Christopher Hooker
Dal Marcus Johannes Henricus Van
Original Assignee
Imec
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imec, Nxp Bv filed Critical Imec
Application granted granted Critical
Publication of ATE451718T1 publication Critical patent/ATE451718T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H10D64/0132—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN the conductor being a metallic silicide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/0137—Manufacturing their gate conductors the gate conductors being silicided
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
AT04077816T 2003-10-17 2004-10-13 Herstellungsverfahren für halbleiterbauelemente mit silizidierten elektroden ATE451718T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
BE2003/0548A BE1015723A4 (nl) 2003-10-17 2003-10-17 Werkwijze voor het vervaardigen van halfgeleiderinrichtingen met gesilicideerde elektroden.

Publications (1)

Publication Number Publication Date
ATE451718T1 true ATE451718T1 (de) 2009-12-15

Family

ID=34318708

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04077816T ATE451718T1 (de) 2003-10-17 2004-10-13 Herstellungsverfahren für halbleiterbauelemente mit silizidierten elektroden

Country Status (8)

Country Link
US (2) US7226827B2 (de)
EP (1) EP1524688B1 (de)
JP (1) JP4994585B2 (de)
CN (1) CN1627502A (de)
AT (1) ATE451718T1 (de)
BE (1) BE1015723A4 (de)
DE (1) DE602004024490D1 (de)
TW (1) TWI242263B (de)

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JP5015446B2 (ja) * 2005-05-16 2012-08-29 アイメック 二重の完全ケイ化ゲートを形成する方法と前記方法によって得られたデバイス
JP2007019395A (ja) * 2005-07-11 2007-01-25 Renesas Technology Corp Ｍｏｓ構造を有する半導体装置及びその製造方法
JP2007019400A (ja) * 2005-07-11 2007-01-25 Renesas Technology Corp Ｍｏｓ構造を有する半導体装置およびその製造方法
JP4784734B2 (ja) * 2005-09-12 2011-10-05 日本電気株式会社 半導体装置及びその製造方法
JP2009509324A (ja) * 2005-09-15 2009-03-05 エヌエックスピー ビー ヴィ 半導体デバイスおよびその製造方法
JP2009509325A (ja) * 2005-09-15 2009-03-05 エヌエックスピー ビー ヴィ 半導体デバイスおよびその製造方法
JP2007123548A (ja) * 2005-10-28 2007-05-17 Renesas Technology Corp 半導体装置の製造方法
JP2009516910A (ja) * 2005-11-21 2009-04-23 フリースケール セミコンダクター インコーポレイテッド サリサイド層を有する半導体装置を形成する方法
US20090045469A1 (en) * 2005-11-28 2009-02-19 Kensuke Takahashi Semiconductor Device and Manufacturing Method Thereof
JP2007158065A (ja) 2005-12-06 2007-06-21 Nec Electronics Corp 半導体装置の製造方法および半導体装置
JP4755894B2 (ja) * 2005-12-16 2011-08-24 株式会社東芝 半導体装置およびその製造方法
JP2007214436A (ja) * 2006-02-10 2007-08-23 Tokyo Electron Ltd 半導体装置の製造方法および半導体装置
KR100729366B1 (ko) * 2006-05-19 2007-06-15 삼성전자주식회사 반도체 장치 및 그 형성 방법
JP5280843B2 (ja) * 2006-05-25 2013-09-04 ルネサスエレクトロニクス株式会社 金属化合物層の形成方法、及び金属化合物層の形成装置
JP4920310B2 (ja) * 2006-05-30 2012-04-18 株式会社東芝 半導体装置およびその製造方法
JP2007324230A (ja) * 2006-05-30 2007-12-13 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP2008016538A (ja) * 2006-07-04 2008-01-24 Renesas Technology Corp Ｍｏｓ構造を有する半導体装置及びその製造方法
WO2008013125A1 (en) * 2006-07-25 2008-01-31 Nec Corporation Semiconductor device and method for manufacturing same
CN101523593B (zh) * 2006-09-29 2012-05-23 瑞萨电子株式会社 半导体装置制造方法以及半导体装置
EP1928021A1 (de) * 2006-11-29 2008-06-04 Interuniversitair Microelektronica Centrum (IMEC) Herstellungsverfahren einer Halbleitervorrichtung mit vollständigem Dual-Silizidgate
JP2009027083A (ja) 2007-07-23 2009-02-05 Toshiba Corp 半導体装置及びその製造方法
JP2009044051A (ja) * 2007-08-10 2009-02-26 Panasonic Corp 半導体装置及びその製造方法
US20090053883A1 (en) * 2007-08-24 2009-02-26 Texas Instruments Incorporated Method of setting a work function of a fully silicided semiconductor device, and related device
WO2009133509A1 (en) * 2008-04-29 2009-11-05 Nxp B.V. Integrated circuit manufacturing method and integrated circuit
US8304841B2 (en) * 2009-09-14 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate transistor, integrated circuits, systems, and fabrication methods thereof
TWI550828B (zh) * 2011-06-10 2016-09-21 住友化學股份有限公司 半導體裝置、半導體基板、半導體基板之製造方法及半導體裝置之製造方法
CN103137475B (zh) * 2011-11-23 2015-09-16 中国科学院微电子研究所 一种半导体结构及其制造方法
CN104952734B (zh) * 2015-07-16 2020-01-24 矽力杰半导体技术(杭州)有限公司 半导体结构及其制造方法

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Also Published As

Publication number Publication date
TW200522270A (en) 2005-07-01
JP2005123625A (ja) 2005-05-12
JP4994585B2 (ja) 2012-08-08
BE1015723A4 (nl) 2005-07-05
TWI242263B (en) 2005-10-21
EP1524688A1 (de) 2005-04-20
US20070215951A1 (en) 2007-09-20
CN1627502A (zh) 2005-06-15
EP1524688B1 (de) 2009-12-09
US7226827B2 (en) 2007-06-05
DE602004024490D1 (de) 2010-01-21
US20050145943A1 (en) 2005-07-07

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