ATE456092T1 - Verarbeitungssystem mit mehrheitsentscheidung - Google Patents

Verarbeitungssystem mit mehrheitsentscheidung

Info

Publication number
ATE456092T1
ATE456092T1 AT01108430T AT01108430T ATE456092T1 AT E456092 T1 ATE456092 T1 AT E456092T1 AT 01108430 T AT01108430 T AT 01108430T AT 01108430 T AT01108430 T AT 01108430T AT E456092 T1 ATE456092 T1 AT E456092T1
Authority
AT
Austria
Prior art keywords
processor
groupings
processor groupings
voter
coupled
Prior art date
Application number
AT01108430T
Other languages
English (en)
Inventor
Kirk Kohnen
Harry Chow
Bret M Botzong
Original Assignee
Boeing Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Boeing Co filed Critical Boeing Co
Application granted granted Critical
Publication of ATE456092T1 publication Critical patent/ATE456092T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/18Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • G06F11/184Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components where the redundant components implement processing functionality
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1675Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1679Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/18Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • G06F11/184Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components where the redundant components implement processing functionality
    • G06F11/185Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components where the redundant components implement processing functionality and the voting is itself performed redundantly

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Control By Computers (AREA)
AT01108430T 2000-04-11 2001-04-04 Verarbeitungssystem mit mehrheitsentscheidung ATE456092T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US54693100A 2000-04-11 2000-04-11

Publications (1)

Publication Number Publication Date
ATE456092T1 true ATE456092T1 (de) 2010-02-15

Family

ID=24182610

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01108430T ATE456092T1 (de) 2000-04-11 2001-04-04 Verarbeitungssystem mit mehrheitsentscheidung

Country Status (3)

Country Link
EP (1) EP1146423B1 (de)
AT (1) ATE456092T1 (de)
DE (1) DE60141096D1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7016946B2 (en) * 2001-07-05 2006-03-21 Sun Microsystems, Inc. Method and system for establishing a quorum for a geographically distributed cluster of computers
US6938183B2 (en) * 2001-09-21 2005-08-30 The Boeing Company Fault tolerant processing architecture
US9312133B2 (en) 2011-08-25 2016-04-12 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US9378956B2 (en) 2011-08-25 2016-06-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US9378955B2 (en) 2011-08-25 2016-06-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
WO2013028973A1 (en) * 2011-08-25 2013-02-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US9396947B2 (en) 2011-08-25 2016-07-19 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
RU2493586C2 (ru) * 2011-12-12 2013-09-20 Федеральное государственное военное образовательное учреждение высшего профессионального образования "Военный авиационный инженерный университет" (г. Воронеж) Министерства обороны Российской Федерации Устройство восстановления работоспособности системы, резервированной с помощью мажоритарных элементов
US9256426B2 (en) 2012-09-14 2016-02-09 General Electric Company Controlling total number of instructions executed to a desired number after iterations of monitoring for successively less number of instructions until a predetermined time period elapse
US9342358B2 (en) 2012-09-14 2016-05-17 General Electric Company System and method for synchronizing processor instruction execution
WO2014205114A1 (en) * 2013-06-18 2014-12-24 Brigham Young University Automated circuit triplication method and system
RU2563798C1 (ru) * 2014-05-19 2015-09-20 Российская Федерация, от имени которой выступает Министерство обороны Российской Федерации Устройство восстановления работоспособности резервированной системы с помощью мажоритарных элементов
GB2555627B (en) * 2016-11-04 2019-02-20 Advanced Risc Mach Ltd Error detection
CN107291570B (zh) * 2017-06-23 2020-01-07 哈尔滨工业大学 基于Zynq-7000的片上存储器抗单粒子翻转防护方法
CN111381982B (zh) * 2020-03-04 2023-05-09 上海航天控制技术研究所 一种适用于火星探测的三计算机数据交互与表决方法
CN111427727B (zh) * 2020-03-04 2023-04-14 上海航天控制技术研究所 一种火星探测三计算机基于数据敏感度及类别的表决方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2093614B (en) * 1981-02-19 1984-10-17 Plessey Co Ltd Triply redundant microprocessor system
JP3063334B2 (ja) * 1991-12-19 2000-07-12 日本電気株式会社 高信頼度化情報処理装置

Also Published As

Publication number Publication date
EP1146423B1 (de) 2010-01-20
DE60141096D1 (de) 2010-03-11
EP1146423A3 (de) 2007-12-26
EP1146423A2 (de) 2001-10-17

Similar Documents

Publication Publication Date Title
DE60141096D1 (de) Verarbeitungssystem mit Mehrheitsentscheidung
US5931959A (en) Dynamically reconfigurable FPGA apparatus and method for multiprocessing and fault tolerance
US5845060A (en) High-performance fault tolerant computer system with clock length synchronization of loosely coupled processors
DK1625484T3 (da) Selvkorrigerende computer
US20110225475A1 (en) Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes
Carter et al. Design techniques for cross-layer resilience
TW366447B (en) Fault tolerant computer system
DE60331771D1 (de) Mechanismus auf dem chip für einen hochzuverlässigkeitsprozessor
CN103262045A (zh) 具有容错架构的微处理器系统
DE3485467D1 (de) Selbstpruefende rechnerschaltungsanordnung.
CN103500125B (zh) 一种基于fpga的抗辐射的数据处理系统及方法
DE69528468D1 (de) Verfahren und vorrichtung für fehlertoleranten taktgeber mit dynamischer rekonfiguration
CN101120320A (zh) 在具有至少两个执行单元的计算机系统中进行模式转换的设备和方法
Doran et al. Dynamic lockstep processors for applications with functional safety relevance
Nazar et al. Fine-grained fast field-programmable gate array scrubbing
US20080320340A1 (en) Method and Device for Performing Switchover Operations and for Comparing Data in a Computer System Having at Least Three Execution Units
CN114544153A (zh) 按键板及旋转编码器的检测方法与检测电路、显示装置
US11982984B2 (en) Automation system for monitoring a safety-critical process
JPH06161798A (ja) 情報処理装置
EP3367242B1 (de) Fehlererkennungsverfahren in einem mikrocontroller
Gericota et al. A self-healing real-time system based on run-time self-reconfiguration
Andjelković et al. A Resilient Processing Platform for 6G Wireless Communication Networks
Rogenmoser et al. Sentrycore: A RISC-V co-processor system for safe, real-time control applications
JPS60198645A (ja) デ−タ処理システム
Börcsök et al. Safe-system-on-chip for functional safety

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties