ATE458274T1 - Tiefgrabenisolationsstrukturen in integrierten halbleiterbauelementen - Google Patents

Tiefgrabenisolationsstrukturen in integrierten halbleiterbauelementen

Info

Publication number
ATE458274T1
ATE458274T1 AT07012746T AT07012746T ATE458274T1 AT E458274 T1 ATE458274 T1 AT E458274T1 AT 07012746 T AT07012746 T AT 07012746T AT 07012746 T AT07012746 T AT 07012746T AT E458274 T1 ATE458274 T1 AT E458274T1
Authority
AT
Austria
Prior art keywords
layer
conductivity type
isolation trench
integrated semiconductor
trench isolation
Prior art date
Application number
AT07012746T
Other languages
English (en)
Inventor
Filip Bauwens
Joris Baele
Original Assignee
Semiconductor Components Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Components Ind filed Critical Semiconductor Components Ind
Application granted granted Critical
Publication of ATE458274T1 publication Critical patent/ATE458274T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials

Landscapes

  • Element Separation (AREA)
AT07012746T 2007-06-29 2007-06-29 Tiefgrabenisolationsstrukturen in integrierten halbleiterbauelementen ATE458274T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP07012746A EP2009686B1 (de) 2007-06-29 2007-06-29 Tiefgrabenisolationsstrukturen in integrierten Halbleiterbauelementen

Publications (1)

Publication Number Publication Date
ATE458274T1 true ATE458274T1 (de) 2010-03-15

Family

ID=38604852

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07012746T ATE458274T1 (de) 2007-06-29 2007-06-29 Tiefgrabenisolationsstrukturen in integrierten halbleiterbauelementen

Country Status (4)

Country Link
US (1) US8115273B2 (de)
EP (1) EP2009686B1 (de)
AT (1) ATE458274T1 (de)
DE (1) DE602007004839D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007129085A (ja) * 2005-11-04 2007-05-24 Texas Instr Japan Ltd 半導体装置及びその製造方法
JP5010660B2 (ja) * 2009-09-25 2012-08-29 株式会社東芝 半導体装置およびその製造方法
US8673723B1 (en) 2013-02-07 2014-03-18 Globalfoundries Inc. Methods of forming isolation regions for FinFET semiconductor devices
US9696736B2 (en) 2013-03-15 2017-07-04 Fairchild Semiconductor Corporation Two-terminal current limiter and apparatus thereof
US9679890B2 (en) * 2013-08-09 2017-06-13 Fairchild Semiconductor Corporation Junction-less insulated gate current limiter device
US9735147B2 (en) 2014-09-15 2017-08-15 Fairchild Semiconductor Corporation Fast and stable ultra low drop-out (LDO) voltage clamp device
US20170373142A1 (en) * 2016-06-23 2017-12-28 Littelfuse, Inc. Semiconductor device having side-diffused trench plug
US10607880B2 (en) * 2018-08-30 2020-03-31 Nxp Usa, Inc. Die with buried doped isolation region

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4534826A (en) * 1983-12-29 1985-08-13 Ibm Corporation Trench etch process for dielectric isolation
JP3360970B2 (ja) * 1995-05-22 2003-01-07 株式会社東芝 半導体装置の製造方法
US6734524B1 (en) * 2002-12-31 2004-05-11 Motorola, Inc. Electronic component and method of manufacturing same
US7491618B2 (en) * 2006-01-26 2009-02-17 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a conductive region

Also Published As

Publication number Publication date
EP2009686A1 (de) 2008-12-31
DE602007004839D1 (de) 2010-04-01
US20090039460A1 (en) 2009-02-12
EP2009686B1 (de) 2010-02-17
US8115273B2 (en) 2012-02-14

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Legal Events

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