ATE461482T1 - Mehrprozessorsystem und programmausführungsverfahren in dem system - Google Patents

Mehrprozessorsystem und programmausführungsverfahren in dem system

Info

Publication number
ATE461482T1
ATE461482T1 AT05805443T AT05805443T ATE461482T1 AT E461482 T1 ATE461482 T1 AT E461482T1 AT 05805443 T AT05805443 T AT 05805443T AT 05805443 T AT05805443 T AT 05805443T AT E461482 T1 ATE461482 T1 AT E461482T1
Authority
AT
Austria
Prior art keywords
processor
interrupt
address
generation unit
predetermined
Prior art date
Application number
AT05805443T
Other languages
English (en)
Inventor
Shinji Noda
Takeshi Kono
Original Assignee
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc filed Critical Sony Computer Entertainment Inc
Application granted granted Critical
Publication of ATE461482T1 publication Critical patent/ATE461482T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)
  • Stored Programmes (AREA)
  • Exchange Systems With Centralized Control (AREA)
AT05805443T 2004-12-03 2005-10-31 Mehrprozessorsystem und programmausführungsverfahren in dem system ATE461482T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004350702A JP3768516B1 (ja) 2004-12-03 2004-12-03 マルチプロセッサシステムとそのシステムにおけるプログラム実行方法
PCT/JP2005/020000 WO2006059444A1 (ja) 2004-12-03 2005-10-31 マルチプロセッサシステムとそのシステムにおけるプログラム実行方法

Publications (1)

Publication Number Publication Date
ATE461482T1 true ATE461482T1 (de) 2010-04-15

Family

ID=36383717

Family Applications (2)

Application Number Title Priority Date Filing Date
AT05805443T ATE461482T1 (de) 2004-12-03 2005-10-31 Mehrprozessorsystem und programmausführungsverfahren in dem system
AT09011692T ATE522863T1 (de) 2004-12-03 2005-10-31 Mehrprozessorsystem und programmausführungsverfahren im system

Family Applications After (1)

Application Number Title Priority Date Filing Date
AT09011692T ATE522863T1 (de) 2004-12-03 2005-10-31 Mehrprozessorsystem und programmausführungsverfahren im system

Country Status (6)

Country Link
US (1) US7805596B2 (de)
EP (2) EP1840736B1 (de)
JP (1) JP3768516B1 (de)
AT (2) ATE461482T1 (de)
DE (1) DE602005020063D1 (de)
WO (1) WO2006059444A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8510596B1 (en) * 2006-02-09 2013-08-13 Virsec Systems, Inc. System and methods for run time detection and correction of memory corruption
US8269782B2 (en) * 2006-11-10 2012-09-18 Sony Computer Entertainment Inc. Graphics processing apparatus
JP2008228969A (ja) * 2007-03-20 2008-10-02 Seiko Epson Corp 画像表示装置及び遊技機
JP2009110455A (ja) * 2007-10-31 2009-05-21 Hakko Denki Kk プログラマブル操作表示器、そのプログラム
US8480398B1 (en) * 2007-12-17 2013-07-09 Tamer Yunten Yunten model computer system and lab kit for education
KR20090103070A (ko) * 2008-03-27 2009-10-01 삼성전자주식회사 멀티 링크 아키텍쳐에서 저장 상태정보의 다이렉트전송기능을 갖는 멀티 프로세서 시스템
CA3297972A1 (en) 2016-06-16 2026-03-02 Virsec Systems, Inc. Systems and methods for remediating memory corruption in a computer application

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4459659A (en) 1981-02-04 1984-07-10 Burroughs Corporation Subroutine control circuitry for providing subroutine operations in a data processing system in which tasks are executed on a microprogrammed level
US5706478A (en) * 1994-05-23 1998-01-06 Cirrus Logic, Inc. Display list processor for operating in processor and coprocessor modes
US5784638A (en) * 1996-02-22 1998-07-21 International Business Machines Corporation Computer system supporting control transfers between two architectures
US6505290B1 (en) * 1997-09-05 2003-01-07 Motorola, Inc. Method and apparatus for interfacing a processor to a coprocessor
US6167504A (en) * 1998-07-24 2000-12-26 Sun Microsystems, Inc. Method, apparatus and computer program product for processing stack related exception traps
US6807620B1 (en) * 2000-02-11 2004-10-19 Sony Computer Entertainment Inc. Game system with graphics processor
JP3338043B2 (ja) 2000-11-02 2002-10-28 株式会社ソニー・コンピュータエンタテインメント 並列演算装置、エンタテインメント装置、演算処理方法、コンピュータプログラム、半導体デバイス
JP2003036169A (ja) 2001-07-25 2003-02-07 Nec Software Tohoku Ltd 複数の小規模プロセッサによって並列処理を行なうシングルチップマイクロプロセッサ
US7024538B2 (en) * 2001-12-21 2006-04-04 Hewlett-Packard Development Company, L.P. Processor multiple function units executing cycle specifying variable length instruction block and using common target block address updated pointers
US6671196B2 (en) * 2002-02-28 2003-12-30 Sun Microsystems, Inc. Register stack in cache memory
US6996677B2 (en) * 2002-11-25 2006-02-07 Nortel Networks Limited Method and apparatus for protecting memory stacks
JP4518564B2 (ja) * 2003-09-04 2010-08-04 サイエンスパーク株式会社 不正コード実行の防止方法、不正コード実行の防止用プログラム、及び不正コード実行の防止用プログラムの記録媒体

Also Published As

Publication number Publication date
WO2006059444A1 (ja) 2006-06-08
JP3768516B1 (ja) 2006-04-19
US20070283135A1 (en) 2007-12-06
EP2124147B1 (de) 2011-08-31
EP2124147A1 (de) 2009-11-25
DE602005020063D1 (de) 2010-04-29
JP2006163552A (ja) 2006-06-22
EP1840736A1 (de) 2007-10-03
EP1840736B1 (de) 2010-03-17
ATE522863T1 (de) 2011-09-15
US7805596B2 (en) 2010-09-28
EP1840736A4 (de) 2009-04-08

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