ATE461487T1 - Taktsignalerzeugungsverfahren für speicher, die keine impulse erzeugen - Google Patents

Taktsignalerzeugungsverfahren für speicher, die keine impulse erzeugen

Info

Publication number
ATE461487T1
ATE461487T1 AT06839836T AT06839836T ATE461487T1 AT E461487 T1 ATE461487 T1 AT E461487T1 AT 06839836 T AT06839836 T AT 06839836T AT 06839836 T AT06839836 T AT 06839836T AT E461487 T1 ATE461487 T1 AT E461487T1
Authority
AT
Austria
Prior art keywords
clock signal
memory
generate
input
circuit
Prior art date
Application number
AT06839836T
Other languages
English (en)
Inventor
Vaishnav Srinivas
Sanat Kapoor
Srinivas Maddali
Vivek Mohan
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ATE461487T1 publication Critical patent/ATE461487T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Databases & Information Systems (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Television Signal Processing For Recording (AREA)
  • Semiconductor Integrated Circuits (AREA)
AT06839836T 2005-11-10 2006-11-10 Taktsignalerzeugungsverfahren für speicher, die keine impulse erzeugen ATE461487T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US73542105P 2005-11-10 2005-11-10
US11/364,296 US7656743B2 (en) 2005-11-10 2006-02-28 Clock signal generation techniques for memories that do not generate a strobe
PCT/US2006/060797 WO2007059443A2 (en) 2005-11-10 2006-11-10 Clock signal generation techniques for memories that do not generate a strobe

Publications (1)

Publication Number Publication Date
ATE461487T1 true ATE461487T1 (de) 2010-04-15

Family

ID=37891473

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06839836T ATE461487T1 (de) 2005-11-10 2006-11-10 Taktsignalerzeugungsverfahren für speicher, die keine impulse erzeugen

Country Status (8)

Country Link
US (1) US7656743B2 (de)
EP (1) EP1946214B1 (de)
JP (1) JP4891329B2 (de)
KR (1) KR101064855B1 (de)
CN (1) CN101356514B (de)
AT (1) ATE461487T1 (de)
DE (1) DE602006013023D1 (de)
WO (1) WO2007059443A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5092770B2 (ja) * 2008-01-29 2012-12-05 富士通セミコンダクター株式会社 位相ロックループ回路及び遅延ロックループ回路
US8045356B2 (en) * 2009-02-27 2011-10-25 Micron Technology, Inc. Memory modules having daisy chain wiring configurations and filters
US8045402B2 (en) * 2009-06-29 2011-10-25 Arm Limited Assisting write operations to data storage cells
US9442186B2 (en) * 2013-05-13 2016-09-13 Microsoft Technology Licensing, Llc Interference reduction for TOF systems
US10462452B2 (en) 2016-03-16 2019-10-29 Microsoft Technology Licensing, Llc Synchronizing active illumination cameras

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3735277A (en) * 1971-05-27 1973-05-22 North American Rockwell Multiple phase clock generator circuit
US4835403A (en) * 1986-12-30 1989-05-30 Bell & Howell Company Clocked optical sensing apparatus
US4959557A (en) * 1989-05-18 1990-09-25 Compaq Computer Corporation Negative feedback circuit to control the duty cycle of a logic system clock
DE69115898T2 (de) * 1991-07-20 1996-07-11 Ibm Quasisynchronen Informationsübertragung mit Phasenausgleichvorrichtung
US6130550A (en) * 1993-01-08 2000-10-10 Dynalogic Scaleable padframe interface circuit for FPGA yielding improved routability and faster chip layout
JPH06314217A (ja) * 1993-04-28 1994-11-08 Tokyo Electric Co Ltd 電子機器
US5479647A (en) 1993-11-12 1995-12-26 Intel Corporation Clock generation and distribution system for a memory controller with a CPU interface for synchronizing the CPU interface with a microprocessor external to the memory controller
JPH08221315A (ja) * 1995-02-15 1996-08-30 Hitachi Ltd 情報処理装置
JP3463727B2 (ja) * 1997-05-09 2003-11-05 株式会社アドバンテスト クロックパルス伝送回路
US6127865A (en) * 1997-05-23 2000-10-03 Altera Corporation Programmable logic device with logic signal delay compensated clock network
US6466491B2 (en) 2000-05-19 2002-10-15 Fujitsu Limited Memory system and memory controller with reliable data latch operation
JP3783845B2 (ja) * 2001-05-09 2006-06-07 三菱電機株式会社 車載電子制御装置
CN1442980A (zh) * 2002-03-04 2003-09-17 赵达镐 网络交换装置及其操作方法
US6760261B2 (en) 2002-09-25 2004-07-06 Infineon Technologies Ag DQS postamble noise suppression by forcing a minimum pulse length
US6980060B2 (en) * 2003-10-23 2005-12-27 International Business Machines Corporation Adaptive method and apparatus to control loop bandwidth of a phase lock loop
CA2575859A1 (en) * 2004-08-11 2006-02-23 Aureon Laboratories, Inc. Systems and methods for automated diagnosis and grading of tissue images
US7312646B2 (en) * 2005-05-13 2007-12-25 Packet Digital Method and apparatus for controlling switching transients
US7323946B2 (en) * 2005-10-20 2008-01-29 Honeywell International Inc. Lock detect circuit for a phase locked loop

Also Published As

Publication number Publication date
KR20080072908A (ko) 2008-08-07
DE602006013023D1 (de) 2010-04-29
JP2009516270A (ja) 2009-04-16
CN101356514B (zh) 2010-09-15
EP1946214B1 (de) 2010-03-17
EP1946214A2 (de) 2008-07-23
CN101356514A (zh) 2009-01-28
US7656743B2 (en) 2010-02-02
US20070104015A1 (en) 2007-05-10
WO2007059443A3 (en) 2007-07-26
KR101064855B1 (ko) 2011-09-14
JP4891329B2 (ja) 2012-03-07
WO2007059443A2 (en) 2007-05-24

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties