ATE465453T1 - Dma-übertragung von datensätzen und ein exklusives oder (xor) der datensätze - Google Patents

Dma-übertragung von datensätzen und ein exklusives oder (xor) der datensätze

Info

Publication number
ATE465453T1
ATE465453T1 AT06815558T AT06815558T ATE465453T1 AT E465453 T1 ATE465453 T1 AT E465453T1 AT 06815558 T AT06815558 T AT 06815558T AT 06815558 T AT06815558 T AT 06815558T AT E465453 T1 ATE465453 T1 AT E465453T1
Authority
AT
Austria
Prior art keywords
records
data
sets
exclusive
dma transfer
Prior art date
Application number
AT06815558T
Other languages
English (en)
Inventor
Peter Brink
Richard Boyd
Brian Skerry
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE465453T1 publication Critical patent/ATE465453T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2211/00—Indexing scheme relating to details of data-processing equipment not covered by groups G06F3/00 - G06F13/00
    • G06F2211/10—Indexing scheme relating to G06F11/10
    • G06F2211/1002—Indexing scheme relating to G06F11/1076
    • G06F2211/1054—Parity-fast hardware, i.e. dedicated fast hardware for RAID systems with parity

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
AT06815558T 2005-09-30 2006-09-26 Dma-übertragung von datensätzen und ein exklusives oder (xor) der datensätze ATE465453T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/240,757 US8205019B2 (en) 2005-09-30 2005-09-30 DMA transfers of sets of data and an exclusive or (XOR) of the sets of data
PCT/US2006/037645 WO2007041154A1 (en) 2005-09-30 2006-09-26 Dma transfers of sets of data and an exclusive or (xor) of the sets of data

Publications (1)

Publication Number Publication Date
ATE465453T1 true ATE465453T1 (de) 2010-05-15

Family

ID=37460145

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06815558T ATE465453T1 (de) 2005-09-30 2006-09-26 Dma-übertragung von datensätzen und ein exklusives oder (xor) der datensätze

Country Status (6)

Country Link
US (1) US8205019B2 (de)
EP (1) EP1934764B1 (de)
CN (1) CN101273338B (de)
AT (1) ATE465453T1 (de)
DE (1) DE602006013854D1 (de)
WO (1) WO2007041154A1 (de)

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US9720603B1 (en) 2013-03-15 2017-08-01 Bitmicro Networks, Inc. IOC to IOC distributed caching architecture
US9400617B2 (en) 2013-03-15 2016-07-26 Bitmicro Networks, Inc. Hardware-assisted DMA transfer with dependency table configured to permit-in parallel-data drain from cache without processor intervention when filled or drained
US9501436B1 (en) 2013-03-15 2016-11-22 Bitmicro Networks, Inc. Multi-level message passing descriptor
US9971524B1 (en) 2013-03-15 2018-05-15 Bitmicro Networks, Inc. Scatter-gather approach for parallel data transfer in a mass storage system
US9430386B2 (en) 2013-03-15 2016-08-30 Bitmicro Networks, Inc. Multi-leveled cache management in a hybrid storage system
US9798688B1 (en) 2013-03-15 2017-10-24 Bitmicro Networks, Inc. Bus arbitration with routing and failover mechanism
US9734067B1 (en) 2013-03-15 2017-08-15 Bitmicro Networks, Inc. Write buffering
US9858084B2 (en) 2013-03-15 2018-01-02 Bitmicro Networks, Inc. Copying of power-on reset sequencer descriptor from nonvolatile memory to random access memory
US9672178B1 (en) 2013-03-15 2017-06-06 Bitmicro Networks, Inc. Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system
US9875205B1 (en) 2013-03-15 2018-01-23 Bitmicro Networks, Inc. Network of memory systems
US9934045B1 (en) 2013-03-15 2018-04-03 Bitmicro Networks, Inc. Embedded system boot from a storage device
US10489318B1 (en) 2013-03-15 2019-11-26 Bitmicro Networks, Inc. Scatter-gather approach for parallel data transfer in a mass storage system
JP5740016B2 (ja) * 2014-02-14 2015-06-24 株式会社ユニバーサルエンターテインメント 遊技機
US9952991B1 (en) 2014-04-17 2018-04-24 Bitmicro Networks, Inc. Systematic method on queuing of descriptors for multiple flash intelligent DMA engine operation
US10025736B1 (en) 2014-04-17 2018-07-17 Bitmicro Networks, Inc. Exchange message protocol message transmission between two devices
US10078604B1 (en) 2014-04-17 2018-09-18 Bitmicro Networks, Inc. Interrupt coalescing
US10055150B1 (en) 2014-04-17 2018-08-21 Bitmicro Networks, Inc. Writing volatile scattered memory metadata to flash device
US10042792B1 (en) 2014-04-17 2018-08-07 Bitmicro Networks, Inc. Method for transferring and receiving frames across PCI express bus for SSD device
US9811461B1 (en) 2014-04-17 2017-11-07 Bitmicro Networks, Inc. Data storage system
CN106294232B (zh) * 2015-05-21 2019-04-30 深圳市中兴微电子技术有限公司 一种dma控制器及其实现方法
CN105446842B (zh) * 2015-12-03 2019-01-04 南京南瑞继保电气有限公司 一种adi dsp代码在线监视方法
CN107357745A (zh) * 2016-05-09 2017-11-17 飞思卡尔半导体公司 具有算术单元的dma控制器
US10552050B1 (en) 2017-04-07 2020-02-04 Bitmicro Llc Multi-dimensional computer storage system
CN109947368A (zh) * 2019-03-21 2019-06-28 记忆科技(深圳)有限公司 数据可靠性检测方法、装置、计算机设备及存储介质
TWI797554B (zh) * 2021-02-05 2023-04-01 新唐科技股份有限公司 系統單晶片及控制方法
KR20230043408A (ko) 2021-09-24 2023-03-31 삼성전자주식회사 메모리 컨트롤러 및 스토리지 장치
US12306777B1 (en) * 2023-03-30 2025-05-20 Amazon Technologies, Inc. Hierarchical collective compute operations using DMA transfers
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US20250291754A1 (en) * 2024-03-12 2025-09-18 Texas Instruments Incorporated Adaptive Burst Transfer for Direct Memory Access
US20260037463A1 (en) * 2024-07-31 2026-02-05 Nvidia Corporation Systems and methods for performing direct memory access data transfers

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Also Published As

Publication number Publication date
EP1934764A1 (de) 2008-06-25
WO2007041154A1 (en) 2007-04-12
DE602006013854D1 (de) 2010-06-02
CN101273338A (zh) 2008-09-24
CN101273338B (zh) 2011-10-05
US20070079017A1 (en) 2007-04-05
US8205019B2 (en) 2012-06-19
EP1934764B1 (de) 2010-04-21

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