ATE481713T1 - Verfahren und vorrichtung für mehrere zeilen- cache-speicher pro bank - Google Patents

Verfahren und vorrichtung für mehrere zeilen- cache-speicher pro bank

Info

Publication number
ATE481713T1
ATE481713T1 AT04815687T AT04815687T ATE481713T1 AT E481713 T1 ATE481713 T1 AT E481713T1 AT 04815687 T AT04815687 T AT 04815687T AT 04815687 T AT04815687 T AT 04815687T AT E481713 T1 ATE481713 T1 AT E481713T1
Authority
AT
Austria
Prior art keywords
row
cache memory
multiple line
per bank
memory per
Prior art date
Application number
AT04815687T
Other languages
English (en)
Inventor
John Halbert
Robert Ellis
Kuljit Bains
Chris Freeman
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE481713T1 publication Critical patent/ATE481713T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT04815687T 2003-12-30 2004-12-23 Verfahren und vorrichtung für mehrere zeilen- cache-speicher pro bank ATE481713T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/750,038 US7050351B2 (en) 2003-12-30 2003-12-30 Method and apparatus for multiple row caches per bank
PCT/US2004/043672 WO2005066967A1 (en) 2003-12-30 2004-12-23 Method and apparatus for multiple row caches per bank

Publications (1)

Publication Number Publication Date
ATE481713T1 true ATE481713T1 (de) 2010-10-15

Family

ID=34711189

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04815687T ATE481713T1 (de) 2003-12-30 2004-12-23 Verfahren und vorrichtung für mehrere zeilen- cache-speicher pro bank

Country Status (8)

Country Link
US (1) US7050351B2 (de)
EP (1) EP1702333B1 (de)
KR (1) KR100850067B1 (de)
CN (1) CN1890753B (de)
AT (1) ATE481713T1 (de)
DE (1) DE602004029192D1 (de)
TW (1) TWI292159B (de)
WO (1) WO2005066967A1 (de)

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US6990036B2 (en) 2003-12-30 2006-01-24 Intel Corporation Method and apparatus for multiple row caches per bank
DE102004012553A1 (de) * 2004-03-15 2005-10-13 Infineon Technologies Ag Speicherbauelement mit asymmetrischer Kontaktreihe
US8521951B2 (en) * 2008-01-16 2013-08-27 S. Aqua Semiconductor Llc Content addressable memory augmented memory
US20090182977A1 (en) * 2008-01-16 2009-07-16 S. Aqua Semiconductor Llc Cascaded memory arrangement
US8543768B2 (en) 2008-11-13 2013-09-24 International Business Machines Corporation Memory system including a spiral cache
US8527726B2 (en) 2008-11-13 2013-09-03 International Business Machines Corporation Tiled storage array with systolic move-to-front reorganization
KR101551775B1 (ko) * 2009-02-11 2015-09-10 삼성전자 주식회사 개선된 글로벌 입출력라인 프리차아지 스킴을 갖는 반도체 메모리 장치
US9779057B2 (en) 2009-09-11 2017-10-03 Micron Technology, Inc. Autonomous memory architecture
CN102610265A (zh) * 2012-03-26 2012-07-25 北京兆易创新科技有限公司 一种闪存
KR101970712B1 (ko) * 2012-08-23 2019-04-22 삼성전자주식회사 단말기의 데이터 이동장치 및 방법
US9299400B2 (en) 2012-09-28 2016-03-29 Intel Corporation Distributed row hammer tracking
JP6337908B2 (ja) * 2013-11-27 2018-06-06 株式会社ソシオネクスト 半導体記憶装置
US10003675B2 (en) 2013-12-02 2018-06-19 Micron Technology, Inc. Packet processor receiving packets containing instructions, data, and starting location and generating packets containing instructions and data
CN105701040B (zh) * 2014-11-28 2018-12-07 杭州华为数字技术有限公司 一种激活内存的方法及装置
KR102292233B1 (ko) 2015-02-13 2021-08-24 삼성전자주식회사 메모리 장치, 이를 포함하는 메모리 모듈, 및 메모리 시스템
TWI648737B (zh) * 2015-11-19 2019-01-21 鈺創科技股份有限公司 能夠快速寫入資料的記憶體電路
US10474581B2 (en) 2016-03-25 2019-11-12 Micron Technology, Inc. Apparatuses and methods for cache operations
EP3532933B1 (de) 2016-10-31 2022-03-02 Rambus Inc. Hybridspeichermodul
KR102707981B1 (ko) * 2017-02-21 2024-09-23 에스케이하이닉스 주식회사 반도체 메모리 장치
US10049721B1 (en) * 2017-03-27 2018-08-14 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US10838851B2 (en) * 2019-02-28 2020-11-17 International Business Machines Corporation Multi-dimensional accesses in memory
KR102789857B1 (ko) 2020-08-31 2025-04-03 에스케이하이닉스 주식회사 저장 장치 및 그 동작 방법
US11972145B2 (en) * 2021-01-21 2024-04-30 Micron Technology, Inc. Opportunistic data movement

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JPH069114B2 (ja) 1983-06-24 1994-02-02 株式会社東芝 半導体メモリ
US4817054A (en) 1985-12-04 1989-03-28 Advanced Micro Devices, Inc. High speed RAM based data serializers
JPH07122989B2 (ja) 1990-06-27 1995-12-25 株式会社東芝 半導体記憶装置
US5586294A (en) * 1993-03-26 1996-12-17 Digital Equipment Corporation Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffer
US5404331A (en) * 1993-07-30 1995-04-04 Sgs-Thomson Microelectronics, Inc. Redundancy element check in IC memory without programming substitution of redundant elements
JP3135795B2 (ja) 1994-09-22 2001-02-19 東芝マイクロエレクトロニクス株式会社 ダイナミック型メモリ
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Also Published As

Publication number Publication date
TW200534293A (en) 2005-10-16
CN1890753B (zh) 2010-12-22
TWI292159B (en) 2008-01-01
WO2005066967A1 (en) 2005-07-21
EP1702333B1 (de) 2010-09-15
US7050351B2 (en) 2006-05-23
CN1890753A (zh) 2007-01-03
DE602004029192D1 (de) 2010-10-28
KR20060114361A (ko) 2006-11-06
US20050146975A1 (en) 2005-07-07
EP1702333A1 (de) 2006-09-20
KR100850067B1 (ko) 2008-08-04

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