ATE481734T1 - Selektive verbindung bei der ic-kapselung - Google Patents

Selektive verbindung bei der ic-kapselung

Info

Publication number
ATE481734T1
ATE481734T1 AT03798966T AT03798966T ATE481734T1 AT E481734 T1 ATE481734 T1 AT E481734T1 AT 03798966 T AT03798966 T AT 03798966T AT 03798966 T AT03798966 T AT 03798966T AT E481734 T1 ATE481734 T1 AT E481734T1
Authority
AT
Austria
Prior art keywords
encapsulation
selective connection
displaced
split
array
Prior art date
Application number
AT03798966T
Other languages
English (en)
Inventor
Stephen Macquarrie
Irving Memis
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE481734T1 publication Critical patent/ATE481734T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/092—Adapting interconnections, e.g. making engineering charges, repairing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0256—Electrical insulation details, e.g. around high voltage areas
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Control And Other Processes For Unpacking Of Materials (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)
AT03798966T 2002-10-01 2003-09-15 Selektive verbindung bei der ic-kapselung ATE481734T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/262,753 US6650016B1 (en) 2002-10-01 2002-10-01 Selective C4 connection in IC packaging
PCT/GB2003/003995 WO2004032222A1 (en) 2002-10-01 2003-09-15 Selective connection in ic packaging

Publications (1)

Publication Number Publication Date
ATE481734T1 true ATE481734T1 (de) 2010-10-15

Family

ID=29420145

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03798966T ATE481734T1 (de) 2002-10-01 2003-09-15 Selektive verbindung bei der ic-kapselung

Country Status (10)

Country Link
US (1) US6650016B1 (de)
EP (1) EP1547142B1 (de)
JP (1) JP4536515B2 (de)
KR (1) KR100633495B1 (de)
CN (1) CN1326222C (de)
AT (1) ATE481734T1 (de)
AU (1) AU2003263368A1 (de)
DE (1) DE60334230D1 (de)
TW (1) TWI226691B (de)
WO (1) WO2004032222A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100576156B1 (ko) * 2003-10-22 2006-05-03 삼성전자주식회사 댐이 형성된 반도체 장치 및 그 반도체 장치의 실장 구조
FR2918212B1 (fr) * 2007-06-27 2009-09-25 Fr De Detecteurs Infrarouges S Procede pour la realisation d'une matrice de rayonnements electromagnetiques et procede pour remplacer un module elementaire d'une telle matrice de detection.
US20090294971A1 (en) * 2008-06-02 2009-12-03 International Business Machines Corporation Electroless nickel leveling of lga pad sites for high performance organic lga
KR101485105B1 (ko) * 2008-07-15 2015-01-23 삼성전자주식회사 반도체 패키지
US9059106B2 (en) 2012-10-31 2015-06-16 International Business Machines Corporation Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip
US9773724B2 (en) * 2013-01-29 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and semiconductor device packages
JP6032070B2 (ja) * 2013-03-13 2016-11-24 ソニー株式会社 半導体装置、半導体装置の製造方法
KR102207273B1 (ko) * 2014-01-29 2021-01-25 삼성전기주식회사 패키지 기판
KR102214512B1 (ko) * 2014-07-04 2021-02-09 삼성전자 주식회사 인쇄회로기판 및 이를 이용한 반도체 패키지
US10244632B2 (en) 2017-03-02 2019-03-26 Intel Corporation Solder resist layer structures for terminating de-featured components and methods of making the same

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4582722A (en) * 1984-10-30 1986-04-15 International Business Machines Corporation Diffusion isolation layer for maskless cladding process
JPS62194652A (ja) * 1986-02-21 1987-08-27 Hitachi Ltd 半導体装置
US4663186A (en) * 1986-04-24 1987-05-05 International Business Machines Corporation Screenable paste for use as a barrier layer on a substrate during maskless cladding
JPS6473696A (en) * 1987-09-14 1989-03-17 Canon Kk Printed-circuit board
JP2810666B2 (ja) * 1988-01-21 1998-10-15 沖電気工業株式会社 フリップチップ型半導体装置及びその製造方法
US5400950A (en) * 1994-02-22 1995-03-28 Delco Electronics Corporation Method for controlling solder bump height for flip chip integrated circuit devices
JPH07273243A (ja) * 1994-03-30 1995-10-20 Toshiba Corp 半導体パッケージ
KR100194130B1 (ko) * 1994-03-30 1999-06-15 니시무로 타이죠 반도체 패키지
JPH07302858A (ja) * 1994-04-28 1995-11-14 Toshiba Corp 半導体パッケージ
WO1996037913A1 (en) * 1995-05-22 1996-11-28 Hitachi Chemical Company, Ltd. Semiconductor device having a semiconductor chip electrically connected to a wiring substrate
KR0157906B1 (ko) * 1995-10-19 1998-12-01 문정환 더미볼을 이용한 비지에이 패키지 및 그 보수방법
US5872393A (en) * 1995-10-30 1999-02-16 Matsushita Electric Industrial Co., Ltd. RF semiconductor device and a method for manufacturing the same
JPH11177225A (ja) * 1997-12-15 1999-07-02 Toshiba Corp プリント基板
KR100265563B1 (ko) * 1998-06-29 2000-09-15 김영환 볼 그리드 어레이 패키지 및 그의 제조 방법
US6242815B1 (en) * 1999-12-07 2001-06-05 Advanced Semiconductor Engineering, Inc. Flexible substrate based ball grid array (BGA) package
US6229219B1 (en) 2000-03-29 2001-05-08 Advanced Micro Devices, Inc. Flip chip package compatible with multiple die footprints and method of assembling the same

Also Published As

Publication number Publication date
CN1669134A (zh) 2005-09-14
JP4536515B2 (ja) 2010-09-01
WO2004032222A1 (en) 2004-04-15
US6650016B1 (en) 2003-11-18
DE60334230D1 (de) 2010-10-28
TW200406050A (en) 2004-04-16
CN1326222C (zh) 2007-07-11
AU2003263368A1 (en) 2004-04-23
EP1547142A1 (de) 2005-06-29
KR100633495B1 (ko) 2006-10-16
TWI226691B (en) 2005-01-11
JP2006501661A (ja) 2006-01-12
EP1547142B1 (de) 2010-09-15
KR20050037599A (ko) 2005-04-22

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Legal Events

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