ATE485525T1 - Prüfbare integrierte schaltung und verfahren zur generierung von testdaten - Google Patents

Prüfbare integrierte schaltung und verfahren zur generierung von testdaten

Info

Publication number
ATE485525T1
ATE485525T1 AT08737705T AT08737705T ATE485525T1 AT E485525 T1 ATE485525 T1 AT E485525T1 AT 08737705 T AT08737705 T AT 08737705T AT 08737705 T AT08737705 T AT 08737705T AT E485525 T1 ATE485525 T1 AT E485525T1
Authority
AT
Austria
Prior art keywords
masking
outputs
test
integrated circuit
cycles
Prior art date
Application number
AT08737705T
Other languages
English (en)
Inventor
Friedrich Hapke
Michael Wittke
Juergen Schloeffel
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE485525T1 publication Critical patent/ATE485525T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AT08737705T 2007-04-05 2008-04-03 Prüfbare integrierte schaltung und verfahren zur generierung von testdaten ATE485525T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07105771 2007-04-05
PCT/IB2008/051250 WO2008122937A1 (en) 2007-04-05 2008-04-03 Testable integrated circuit and test data generation method

Publications (1)

Publication Number Publication Date
ATE485525T1 true ATE485525T1 (de) 2010-11-15

Family

ID=39691072

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08737705T ATE485525T1 (de) 2007-04-05 2008-04-03 Prüfbare integrierte schaltung und verfahren zur generierung von testdaten

Country Status (5)

Country Link
US (1) US8250420B2 (de)
EP (1) EP2135104B1 (de)
AT (1) ATE485525T1 (de)
DE (1) DE602008003105D1 (de)
WO (1) WO2008122937A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009150726A (ja) * 2007-12-19 2009-07-09 Panasonic Corp 半導体装置
WO2010060012A1 (en) * 2008-11-23 2010-05-27 Mentor Graphics Corporation On-chip logic to support in-field or post-tape-out x-masking in bist designs
US8103925B2 (en) * 2008-11-24 2012-01-24 Mentor Graphics Corporation On-chip logic to support compressed X-masking for BIST
US8112686B2 (en) * 2008-12-01 2012-02-07 Mentor Graphics Corporation Deterministic logic built-in self-test stimuli generation
US9448282B1 (en) * 2014-02-12 2016-09-20 Cadence Design Systems, Inc. System and method for bit-wise selective masking of scan vectors for X-value tolerant built-in self test
GB201711055D0 (en) * 2017-07-10 2017-08-23 Accelercomm Ltd Electronic device with bit pattern generation, integrated circuit and method for polar coding
US11422186B1 (en) * 2019-06-20 2022-08-23 Synopsys, Inc. Per-shift X-tolerant logic built-in self-test
CN113671360B (zh) * 2020-05-13 2024-06-18 圣邦微电子（北京）股份有限公司 I2c接口器件测试方法、装置及i2c接口器件
US11782092B1 (en) * 2022-05-18 2023-10-10 Stmicroelectronics International N.V. Scan compression through pin data encoding
US12480993B2 (en) 2024-03-18 2025-11-25 Stmicroelectronics International N.V. Low pin count scan with no dedicated scan enable pin

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5826071A (en) * 1995-08-31 1998-10-20 Advanced Micro Devices, Inc. Parallel mask decoder and method for generating said mask
US6173386B1 (en) * 1998-12-14 2001-01-09 Cisco Technology, Inc. Parallel processor with debug capability
US6557129B1 (en) 1999-11-23 2003-04-29 Janusz Rajski Method and apparatus for selectively compacting test responses
JP2001249164A (ja) 2000-03-03 2001-09-14 Hitachi Ltd 組み込み型自己テスト回路内臓ｌｓｉ
DE10038327A1 (de) 2000-08-05 2002-02-14 Philips Corp Intellectual Pty Integrierter Schaltkreis mit Selbsttest-Schaltung
JP4228061B2 (ja) * 2000-12-07 2009-02-25 富士通マイクロエレクトロニクス株式会社 集積回路の試験装置および試験方法
US7032148B2 (en) 2003-07-07 2006-04-18 Syntest Technologies, Inc. Mask network design for scan-based integrated circuits
DE602004009329T2 (de) * 2003-09-26 2008-07-10 Nxp B.V. Verfahren und system zum selektiven maskieren von testantworten
EP2677328B1 (de) * 2006-02-17 2015-07-29 Mentor Graphics Corporation Mehrstufige Testreaktionsverdichter
US7404126B2 (en) * 2006-03-29 2008-07-22 Texas Instruments Incorporated Scan tests tolerant to indeterminate states when employing signature analysis to analyze test outputs

Also Published As

Publication number Publication date
US8250420B2 (en) 2012-08-21
US20100117658A1 (en) 2010-05-13
WO2008122937A1 (en) 2008-10-16
EP2135104A1 (de) 2009-12-23
EP2135104B1 (de) 2010-10-20
DE602008003105D1 (de) 2010-12-02

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Legal Events

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